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Re: [dfa-branch] DFA pipeline description for SH4

Naveen Sharma wrote:
> Hi,
> > > >> 26th Sept,2001,Naveen  Sharma Wrote:
> > > > > I have been interested by the discussion on the new DFA
> > > > based scheduler
> > > > > developed by you for gcc.I plan to study the
> > implementation of the
> > > > > scheduler and would like to contribute further for the
> > scheduler.
> > > > > My friend,Nitin Gupta,would  be joining me in the effort.
> > > > > At present we are interested in using the DFA based scheduler
> > > > > for SH4 target which might benefit from the new scheduler.
> > I've never worked on SH4.  If this is a not OOO processor
> > than you might have an improvement.
> We would like to submit DFA pipeline description for SH4 processor.
> We would also like to inform about test results that we have measured
> with this patch.Some benchmarks notably SLALOM
> (
> have shown (12%-13%)improvement.

It is a great news for me.  Thank you for your work!

> Meanwhile there are certain applications which have slightly
> degraded performance.We are analysing them and would update
> you regarding them.

  Usually, it is well known conflict between insn schedulers and
register allocators.  Dfa-based scheduler improves fine-grain
parallelism by moving some insns further which results in increasing
register pressure and spilling registers.  So you could check additional
spilling registers the first to find the reason of the degradation.  The
simplest solution of the problem could be using register pressure in
insn scheduler heuristics.


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