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altivec cleanups


a potpourri of changes.  things seem to be stabilizing.  a native ppc
build with and without --enable-altivec have the same failures, no
regressions (for c/c+).

changes:

    i'm adding support for --enable-altivec.  i plan to remove the
    powerpc-unknown-linux-gnualtivec triplet in favor of just doing a
    native build with --enable-altivec.  this seems cleaner.
    
    new altivec.h for use with --enable-altivec
        
    fix typo in linuxaltivec.h (this file should hopefully go away soon
    now that we have --enable-altivec).
        
    vrsave sets are now unspec volatile.  i ran into more probs with
    flow trying to delete pro/epilogue insns.  in one of the cases, we
    had a non-returning function that used setjmp().  gcc decided to not
    generate the epilogue since it was not necessary, but to generate
    the prologue because of setjmp().  this caused a seemingly dead
    store into VRSAVE.  however, VRSAVE is never dead because the OS
    needs it.  so now, pro/epilogue sets of vrsave are unspec volatiles.
    
    there are no vrsave set patterns now.  i followed david's suggestion
    and collapsed these into the movsi pattern.
    
    vrsave added to SPECIAL_REGS
    
    a few minor cleanups.
    
i was finally able to build the entire toolchain (all langs + libraries)
with altivec enabled.

ok?

-- 
Aldy Hernandez			E-mail: aldyh@redhat.com
Professional Gypsy
Red Hat, Inc.

2001-12-18  Aldy Hernandez  <aldyh@redhat.com>

	* config.gcc: Add support for --enable-altivec.

	* config/rs6000/altivec.h: New.

	* config/rs6000/linuxaltivec.h (SUBSUBTARGET_OVERRIDE_OPTIONS):
	Define.  Fix typo.

	* config/rs6000/rs6000.c (vrsave_operation): Change unspec to
	unspec_volatile.
	(generate_set_vrsave): Generate the unspec here instead of calling
	an .md pattern.
	(generate_set_vrsave): Use gen_rtvec.
	(rs6000_emit_prologue): Replace call to gen_get_vrsave with
	gen_rtx_SET.

	* config/rs6000/rs6000.md ("*movsi_internal1"): Add constraints
	for setting special registers.
	("*set_vrsave_internal"): Use unspec_volatile.
	("set_vrsave"): Remove.
	("get_vrsave"): Remove.

	* config/rs6000/rs6000.h (REG_CLASS_CONTENTS): Add vrsave to
	SPECIAL_REGS.

Index: config.gcc
===================================================================
RCS file: /cvs/uberbaum/gcc/config.gcc,v
retrieving revision 1.135
diff -c -p -r1.135 config.gcc
*** config.gcc	2001/12/17 07:33:06	1.135
--- config.gcc	2001/12/19 09:09:28
*************** mips*-*-*)
*** 3459,3464 ****
--- 3459,3468 ----
  	fi
  	;;
  powerpc*-*-* | rs6000-*-*)
+ 	if test x$enable_altivec = xyes
+ 	then
+ 		tm_file="$tm_file rs6000/altivec.h"
+ 	fi
  	case "x$with_cpu" in
  		x)
  			;;
Index: config/rs6000/altivec.h
===================================================================
RCS file: altivec.h
diff -N altivec.h
*** /dev/null	Tue May  5 13:32:27 1998
--- altivec.h	Wed Dec 19 01:09:28 2001
***************
*** 0 ****
--- 1,27 ----
+ /* Target definitions for GNU compiler for PowerPC with AltiVec.
+    Copyright (C) 2001 Free Software Foundation, Inc.
+    Contributed by Aldy Hernandez (aldyh@redhat.com).
+ 
+ This file is part of GNU CC.
+ 
+ GNU CC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+ 
+ GNU CC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with GNU CC; see the file COPYING.  If not, write to
+ the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA.  */
+ 
+ #undef SUBSUBTARGET_OVERRIDE_OPTIONS
+ #define SUBSUBTARGET_OVERRIDE_OPTIONS	\
+ do {					\
+   rs6000_altivec_abi = 1;		\
+   target_flags |= MASK_ALTIVEC;		\
+ } while (0)
Index: config/rs6000/linuxaltivec.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/linuxaltivec.h,v
retrieving revision 1.1
diff -c -p -r1.1 linuxaltivec.h
*** linuxaltivec.h	2001/12/13 23:14:45	1.1
--- linuxaltivec.h	2001/12/19 09:09:28
*************** Boston, MA 02111-1307, USA.  */
*** 27,30 ****
  #undef	TARGET_DEFAULT
  #define	TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_ALTIVEC)
  
! #undef SUBSUBTARGET_OVERRIDE_OPTIONS	rs6000_altivec_abi = 1
--- 27,31 ----
  #undef	TARGET_DEFAULT
  #define	TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_ALTIVEC)
  
! #undef SUBSUBTARGET_OVERRIDE_OPTIONS
! #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.265
diff -c -p -r1.265 rs6000.c
*** rs6000.c	2001/12/17 22:33:39	1.265
--- rs6000.c	2001/12/19 09:09:54
*************** vrsave_operation (op, mode)
*** 4427,4433 ****
    if (count <= 1
        || GET_CODE (XVECEXP (op, 0, 0)) != SET
        || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
!       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
      return 0;
  
    dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
--- 4427,4433 ----
    if (count <= 1
        || GET_CODE (XVECEXP (op, 0, 0)) != SET
        || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
!       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
      return 0;
  
    dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
*************** generate_set_vrsave (reg, info, epilogue
*** 7703,7710 ****
  {
    int nclobs, i;
    rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
  
!   clobs[0] = gen_set_vrsave (reg);
  
    nclobs = 1;
  
--- 7703,7716 ----
  {
    int nclobs, i;
    rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
+   rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
  
!   clobs[0]
!     = gen_rtx_SET (VOIDmode,
! 		   vrsave,
! 		   gen_rtx_UNSPEC_VOLATILE (SImode,
! 					    gen_rtvec (2, reg, vrsave),
! 					    30));
  
    nclobs = 1;
  
*************** generate_set_vrsave (reg, info, epilogue
*** 7731,7742 ****
  	else
  	  {
  	    rtx reg = gen_rtx_REG (V4SImode, i);
- 	    rtvec r = rtvec_alloc (1);
  
- 	    RTVEC_ELT (r, 0) = reg;
- 
  	    clobs[nclobs++]
! 	      = gen_rtx_SET (VOIDmode, reg, gen_rtx_UNSPEC (V4SImode, r, 27));
  	  }
        }
  
--- 7737,7748 ----
  	else
  	  {
  	    rtx reg = gen_rtx_REG (V4SImode, i);
  
  	    clobs[nclobs++]
! 	      = gen_rtx_SET (VOIDmode,
! 			     reg,
! 			     gen_rtx_UNSPEC (V4SImode,
! 					     gen_rtvec (1, reg), 27));
  	  }
        }
  
*************** rs6000_emit_prologue ()
*** 7830,7841 ****
  
    if (TARGET_ALTIVEC && info->vrsave_mask != 0)
      {
!       rtx reg, mem;
        int offset;
  
        /* Get VRSAVE onto a GPR.  */
        reg = gen_rtx_REG (SImode, 12);
!       emit_insn (gen_get_vrsave (reg));
  
        /* Save VRSAVE.  */
        offset = info->vrsave_save_offset + sp_offset;
--- 7836,7848 ----
  
    if (TARGET_ALTIVEC && info->vrsave_mask != 0)
      {
!       rtx reg, mem, vrsave;
        int offset;
  
        /* Get VRSAVE onto a GPR.  */
        reg = gen_rtx_REG (SImode, 12);
!       vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
!       emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
  
        /* Save VRSAVE.  */
        offset = info->vrsave_save_offset + sp_offset;
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.161
diff -c -p -r1.161 rs6000.h
*** rs6000.h	2001/12/17 19:11:13	1.161
--- rs6000.h	2001/12/19 09:10:06
*************** enum reg_class
*** 1121,1127 ****
    { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */	     \
    { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */	     \
    { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
!   { 0x00000000, 0x00000000, 0x00000007, 0x00000000 }, /* SPECIAL_REGS */     \
    { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
    { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */	     \
    { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */	     \
--- 1121,1127 ----
    { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */	     \
    { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */	     \
    { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
!   { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */     \
    { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
    { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */	     \
    { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */	     \
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.148
diff -c -p -r1.148 rs6000.md
*** rs6000.md	2001/12/17 19:11:11	1.148
--- rs6000.md	2001/12/19 09:10:26
***************
*** 7630,7637 ****
     (set_attr "length" "4")])
  
  (define_insn "*movsi_internal1"
!   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
! 	(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
    "gpc_reg_operand (operands[0], SImode)
     || gpc_reg_operand (operands[1], SImode)"
    "@
--- 7630,7637 ----
     (set_attr "length" "4")])
  
  (define_insn "*movsi_internal1"
!   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
! 	(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
    "gpc_reg_operand (operands[0], SImode)
     || gpc_reg_operand (operands[1], SImode)"
    "@
***************
*** 7646,7654 ****
     mf%1 %0
     mt%0 %1
     mt%0 %1
     cror 0,0,0"
!   [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
!    (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
  
  ;; Split a load of a large constant into the appropriate two-insn
  ;; sequence.
--- 7646,7655 ----
     mf%1 %0
     mt%0 %1
     mt%0 %1
+    mt%0 %1
     cror 0,0,0"
!   [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
!    (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
  
  ;; Split a load of a large constant into the appropriate two-insn
  ;; sequence.
***************
*** 13944,13972 ****
     vor %0,%1,%1"
    [(set_attr "type" "altivec")])
  
- ;; Copy VRSAVE into a GPR.
- (define_insn "get_vrsave"
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(unspec:SI [(reg:SI 109)] 28))]
-   "TARGET_ALTIVEC"
-   "mfvrsave %0"
-   [(set_attr "type" "altivec")])
- 
  (define_insn "*set_vrsave_internal"
    [(match_parallel 0 "vrsave_operation"
       [(set (reg:SI 109)
! 	   (unspec:SI [(match_operand:SI 1 "register_operand" "r")
! 		       (reg:SI 109)] 30))])]
    "TARGET_ALTIVEC"
    "mtvrsave %1"
-   [(set_attr "type" "altivec")])
- 
- (define_insn "set_vrsave"
-   [(set (reg:SI 109)
- 	(unspec:SI [(match_operand:SI 0 "register_operand" "r")
- 		    (reg:SI 109)] 30))]
-   "TARGET_ALTIVEC"
-   "mtvrsave %0"
    [(set_attr "type" "altivec")])
  
  ;; Simple binary operations.
--- 13945,13957 ----
     vor %0,%1,%1"
    [(set_attr "type" "altivec")])
  
  (define_insn "*set_vrsave_internal"
    [(match_parallel 0 "vrsave_operation"
       [(set (reg:SI 109)
! 	   (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
! 				(reg:SI 109)] 30))])]
    "TARGET_ALTIVEC"
    "mtvrsave %1"
    [(set_attr "type" "altivec")])
  
  ;; Simple binary operations.


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