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ix86 prefetch support updated (still partly perlimitary?)



Hi,
This adds the prefetch support at the top of configury bits.  It appears
to work, but I guess I need to test it more seriously tommorow.

Bootstrapped/regtested i386

Thu Dec 13 21:57:13 CET 2001  Janis Jognson <janis187@us.ibm.com>
			      Jan Hubicka  <jh@suse.cz>

	* config/i386/i386.h (struct processor_costs): Add new members
	  prefetch_block and simultaneous_prefetches.
	  (PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): New.
	* config/i386/i386.c (processor_costs structs): Add values for
	  prefetch_block and simultaneous_prefetches.
	* config/i386/i386.md (unspec values): Remove values for prefetch
	  operations, which now use the PREFETCH rtx code.
	  (prefetch_sse, prefetch_3dnow, prefetchw): Combine to use new
	  unified prefetch support.
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.345
diff -c -3 -p -r1.345 i386.c
*** i386.c	2001/12/13 11:34:08	1.345
--- i386.c	2001/12/13 20:48:04
*************** struct processor_costs size_cost = {	/* 
*** 81,86 ****
--- 81,88 ----
    {3, 3, 3},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
    3,					/* MMX or SSE register to integer */
+   0,					/* size of prefetch block */
+   0,					/* number of parallel prefetches */
  };
  /* Processor costs (relative to an add) */
  static const 
*************** struct processor_costs i386_cost = {	/* 
*** 116,121 ****
--- 118,125 ----
    {4, 8, 16},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
    3,					/* MMX or SSE register to integer */
+   0,					/* size of prefetch block */
+   0,					/* number of parallel prefetches */
  };
  
  static const 
*************** struct processor_costs i486_cost = {	/* 
*** 150,156 ****
  					   in SImode, DImode and TImode */
    {4, 8, 16},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   3					/* MMX or SSE register to integer */
  };
  
  static const 
--- 154,162 ----
  					   in SImode, DImode and TImode */
    {4, 8, 16},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   3,					/* MMX or SSE register to integer */
!   0,					/* size of prefetch block */
!   0,					/* number of parallel prefetches */
  };
  
  static const 
*************** struct processor_costs pentium_cost = {
*** 185,191 ****
  					   in SImode, DImode and TImode */
    {4, 8, 16},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   3					/* MMX or SSE register to integer */
  };
  
  static const 
--- 191,199 ----
  					   in SImode, DImode and TImode */
    {4, 8, 16},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   3,					/* MMX or SSE register to integer */
!   0,					/* size of prefetch block */
!   0,					/* number of parallel prefetches */
  };
  
  static const 
*************** struct processor_costs pentiumpro_cost =
*** 220,226 ****
  					   in SImode, DImode and TImode */
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   3					/* MMX or SSE register to integer */
  };
  
  static const 
--- 228,236 ----
  					   in SImode, DImode and TImode */
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   3,					/* MMX or SSE register to integer */
!   32,					/* size of prefetch block */
!   6,					/* number of parallel prefetches */
  };
  
  static const 
*************** struct processor_costs k6_cost = {
*** 255,261 ****
  					   in SImode, DImode and TImode */
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   6					/* MMX or SSE register to integer */
  };
  
  static const 
--- 265,273 ----
  					   in SImode, DImode and TImode */
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   6,					/* MMX or SSE register to integer */
!   32,					/* size of prefetch block */
!   1,					/* number of parallel prefetches */
  };
  
  static const 
*************** struct processor_costs athlon_cost = {
*** 290,296 ****
  					   in SImode, DImode and TImode */
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   6					/* MMX or SSE register to integer */
  };
  
  static const 
--- 302,310 ----
  					   in SImode, DImode and TImode */
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
!   6,					/* MMX or SSE register to integer */
!   64,					/* size of prefetch block */
!   6,					/* number of parallel prefetches */
  };
  
  static const 
*************** struct processor_costs pentium4_cost = {
*** 326,331 ****
--- 340,347 ----
    {2, 2, 8},				/* cost of storing SSE registers
  					   in SImode, DImode and TImode */
    10,					/* MMX or SSE register to integer */
+   64,					/* size of prefetch block */
+   6,					/* number of parallel prefetches */
  };
  
  const struct processor_costs *ix86_cost = &pentium_cost;
*************** ix86_expand_builtin (exp, target, subtar
*** 11816,11837 ****
        return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3, arglist, target);
  
      case IX86_BUILTIN_PREFETCH_3DNOW:
-       icode = CODE_FOR_prefetch_3dnow;
-       arg0 = TREE_VALUE (arglist);
-       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
-       mode0 = insn_data[icode].operand[0].mode;
-       pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0));
-       if (! pat)
-         return NULL_RTX;
-       emit_insn (pat);
-       return NULL_RTX;
- 
      case IX86_BUILTIN_PREFETCHW:
!       icode = CODE_FOR_prefetchw;
        arg0 = TREE_VALUE (arglist);
        op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
        mode0 = insn_data[icode].operand[0].mode;
!       pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0));
        if (! pat)
          return NULL_RTX;
        emit_insn (pat);
--- 11839,11851 ----
        return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3, arglist, target);
  
      case IX86_BUILTIN_PREFETCH_3DNOW:
      case IX86_BUILTIN_PREFETCHW:
!       icode = CODE_FOR_prefetch_3dnow;
        arg0 = TREE_VALUE (arglist);
        op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+       op1 = (fcode == IX86_BUILTIN_PREFETCH_3DNOW ? const0_rtx : const1_rtx);
        mode0 = insn_data[icode].operand[0].mode;
!       pat = GEN_FCN (icode) (copy_to_mode_reg (Pmode, op0), op1);
        if (! pat)
          return NULL_RTX;
        emit_insn (pat);
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.h,v
retrieving revision 1.222
diff -c -3 -p -r1.222 i386.h
*** i386.h	2001/12/13 11:34:10	1.222
--- i386.h	2001/12/13 20:48:04
*************** struct processor_costs {
*** 86,91 ****
--- 86,94 ----
  				   in SImode, DImode and TImode*/
    const int mmxsse_to_integer;	/* cost of moving mmxsse register to
  				   integer and vice versa.  */
+   const int prefetch_block;	/* bytes moved to cache for prefetch.  */
+   const int simultaneous_prefetches; /* number of parallel prefetch
+ 				   operations.  */
  };
  
  extern const struct processor_costs *ix86_cost;
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.321
diff -c -3 -p -r1.321 i386.md
*** i386.md	2001/12/10 14:30:11	1.321
--- i386.md	2001/12/13 20:48:09
***************
*** 93,100 ****
  ;; 44 This is a `sfence' operation.
  ;; 45 This is a noop to prevent excessive combiner cleverness.
  ;; 46 This is a `femms' operation.
- ;; 47 This is a `prefetch' (3DNow) operation.
- ;; 48 This is a `prefetchw' operation.
  ;; 49 This is a 'pavgusb' operation.
  ;; 50 This is a `pfrcp' operation.
  ;; 51 This is a `pfrcpit1' operation.
--- 93,98 ----
***************
*** 19333,19342 ****
    [(set_attr "type" "sse")
     (set_attr "memory" "unknown")])
  
  (define_insn "prefetch_sse"
    [(unspec [(match_operand:SI 0 "address_operand" "p")
  	    (match_operand:SI 1 "immediate_operand" "n")] 35)]
!   "TARGET_SSE || TARGET_3DNOW_A"
  {
    switch (INTVAL (operands[1]))
      {
--- 19331,19388 ----
    [(set_attr "type" "sse")
     (set_attr "memory" "unknown")])
  
+ (define_expand "prefetch"
+   [(prefetch (match_operand:SI 0 "address_operand" "p")
+ 	     (match_operand:SI 1 "const_int_operand" "n")
+ 	     (match_operand:SI 2 "const_int_operand" "n"))]
+   "TARGET_PREFETCH_SSE || TARGET_3DNOW"
+   "
+ {
+   int rw = INTVAL (operands[1]);
+   int locality = INTVAL (operands[2]);
+   if (rw != 0 && rw != 1)
+     abort ();
+   if (locality < 0 || locality > 3)
+     abort ();
+   /* Use 3dNOW prefetch in case we are asking for write prefetch not
+      suported by SSE counterpart or the SSE prefetch is not available
+      (K6 machines).  Otherwise use SSE prefetch as it allows specifying
+      of locality.  */
+   if (TARGET_3DNOW
+        && (!TARGET_PREFETCH_SSE || rw))
+     {
+       emit_insn (gen_prefetch_3dnow (operands[0], operands[1]));
+     }
+   else
+     {
+       int i;
+       switch (locality)
+ 	{
+ 	  case 0:	/* No temporal locality.  */
+ 	    i = 0;
+ 	    break;
+ 	  case 1:	/* Lowest level of temporal locality.  */
+ 	    i = 3;
+ 	    break;
+ 	  case 2:	/* Moderate level of temporal locality.  */
+ 	    i = 2;
+ 	    break;
+ 	  case 3:	/* Highest level of temporal locality.  */
+ 	    i = 1;
+ 	    break;
+ 	  default:
+ 	    abort ();	/* We already checked for valid values above.  */
+ 	    break;
+ 	}
+       emit_insn (gen_prefetch_sse (operands[0], GEN_INT (i)));
+     }
+   DONE;
+ }")
+ 
  (define_insn "prefetch_sse"
    [(unspec [(match_operand:SI 0 "address_operand" "p")
  	    (match_operand:SI 1 "immediate_operand" "n")] 35)]
!   "TARGET_PREFETCH_SSE"
  {
    switch (INTVAL (operands[1]))
      {
***************
*** 19512,19526 ****
    [(set_attr "type" "mmx")])
  
  (define_insn "prefetch_3dnow"
!   [(unspec [(match_operand:SI 0 "address_operand" "p")] 47)]
!   "TARGET_3DNOW"
!   "prefetch\\t%a0"
!   [(set_attr "type" "mmx")])
! 
! (define_insn "prefetchw"
!   [(unspec [(match_operand:SI 0 "address_operand" "p")] 48)]
    "TARGET_3DNOW"
!   "prefetchw\\t%a0"
    [(set_attr "type" "mmx")])
  
  (define_insn "pf2id"
--- 19558,19573 ----
    [(set_attr "type" "mmx")])
  
  (define_insn "prefetch_3dnow"
!   [(prefetch (match_operand:SI 0 "address_operand" "p")
! 	     (match_operand:SI 1 "const_int_operand" "n")
! 	     (const_int 0))]
    "TARGET_3DNOW"
! {
!   if (INTVAL (operands[1]) == 0)
!     return "prefetch\t%a0";
!   else
!     return "prefetchw\t%a0";
! }
    [(set_attr "type" "mmx")])
  
  (define_insn "pf2id"


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