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alpha explicit relocs vs divide patterns


A bootstrap with -mexplicit-relocs showed a case in which
the GP reload got scheduled after a divide pattern.  Which
is bad because the divide pattern uses the GP.


r~


        * config/alpha/alpha.md (divmodsi_internal_er): Split, so that
        we represent the address load's dependency on the gp.
        (divmoddi_internal_er): Likewise.
        (divmodsi_internal_er_1, divmoddi_internal_er_1): New.

Index: config/alpha/alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.164
diff -c -p -d -r1.164 alpha.md
*** alpha.md	2001/12/10 22:21:03	1.164
--- alpha.md	2001/12/12 02:51:05
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1190,1196 ****
  ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
  ;; expanded by the assembler.
  
! (define_insn "*divmodsi_internal_er"
    [(set (match_operand:DI 0 "register_operand" "=c")
  	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
  			[(match_operand:DI 1 "register_operand" "a")
--- 1190,1196 ----
  ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
  ;; expanded by the assembler.
  
! (define_insn_and_split "*divmodsi_internal_er"
    [(set (match_operand:DI 0 "register_operand" "=c")
  	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
  			[(match_operand:DI 1 "register_operand" "a")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1199,1207 ****
--- 1199,1249 ----
     (clobber (reg:DI 28))]
    "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
    "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
+   "&& reload_completed"
+   [(parallel [(set (match_dup 0)
+ 		   (sign_extend:DI (match_dup 3)))
+ 	      (use (match_dup 0))
+ 	      (clobber (reg:DI 23))
+ 	      (clobber (reg:DI 28))])]
+ {
+   const char *str;
+   switch (GET_CODE (operands[3]))
+     {
+     case DIV: 
+       str = "__divl";
+       break; 
+     case UDIV:
+       str = "__divlu";
+       break;
+     case MOD:
+       str = "__reml";
+       break;
+     case UMOD:
+       str = "__remlu";
+       break;
+     default:
+       abort ();
+     }
+   emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
+ 				  gen_rtx_SYMBOL_REF (DImode, str),
+ 				  const0_rtx));
+ }
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
  
+ (define_insn "*divmodsi_internal_er_1"
+   [(set (match_operand:DI 0 "register_operand" "=c")
+ 	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
+                         [(match_operand:DI 1 "register_operand" "a")
+                          (match_operand:DI 2 "register_operand" "b")])))
+    (use (match_operand:DI 4 "register_operand" "c"))
+    (clobber (reg:DI 23))
+    (clobber (reg:DI 28))]
+   "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
+   "jsr $23,($27),__%E3"
+   [(set_attr "type" "jsr")
+    (set_attr "length" "4")])
+ 
  (define_insn "*divmodsi_internal"
    [(set (match_operand:DI 0 "register_operand" "=c")
  	(sign_extend:DI (match_operator:SI 3 "divmod_operator"
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1214,1220 ****
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
  
! (define_insn "*divmoddi_internal_er"
    [(set (match_operand:DI 0 "register_operand" "=c")
  	(match_operator:DI 3 "divmod_operator"
  			[(match_operand:DI 1 "register_operand" "a")
--- 1256,1262 ----
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
  
! (define_insn_and_split "*divmoddi_internal_er"
    [(set (match_operand:DI 0 "register_operand" "=c")
  	(match_operator:DI 3 "divmod_operator"
  			[(match_operand:DI 1 "register_operand" "a")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1223,1230 ****
--- 1265,1313 ----
     (clobber (reg:DI 28))]
    "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
    "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
+   "&& reload_completed"
+   [(parallel [(set (match_dup 0) (match_dup 3))
+ 	      (use (match_dup 0))
+ 	      (clobber (reg:DI 23))
+ 	      (clobber (reg:DI 28))])]
+ {
+   const char *str;
+   switch (GET_CODE (operands[3]))
+     {
+     case DIV: 
+       str = "__divq";
+       break; 
+     case UDIV:
+       str = "__divqu";
+       break;
+     case MOD:
+       str = "__remq";
+       break;
+     case UMOD:
+       str = "__remqu";
+       break;
+     default:
+       abort ();
+     }
+   emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
+ 				  gen_rtx_SYMBOL_REF (DImode, str),
+ 				  const0_rtx));
+ }
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
+ 
+ (define_insn "*divmoddi_internal_er_1"
+   [(set (match_operand:DI 0 "register_operand" "=c")
+ 	(match_operator:DI 3 "divmod_operator"
+                         [(match_operand:DI 1 "register_operand" "a")
+                          (match_operand:DI 2 "register_operand" "b")]))
+    (use (match_operand:DI 4 "register_operand" "c"))
+    (clobber (reg:DI 23))
+    (clobber (reg:DI 28))]
+   "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
+   "jsr $23,($27),__%E3"
+   [(set_attr "type" "jsr")
+    (set_attr "length" "4")])
  
  (define_insn "*divmoddi_internal"
    [(set (match_operand:DI 0 "register_operand" "=c")


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