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FIX rs6000 -maix64 -mstring

From: Tom Rix <trix at redhat dot com>
To: gcc-patches at gcc dot gnu dot org
Date: Sat, 08 Dec 2001 21:03:12 -0600
Subject: FIX rs6000 -maix64 -mstring

In the current sources, the combination of  -maix64 -mstring causes 500+
additional failures.
This patch fixes them.

The -mstring is not being exercised because of the setting of
MASK_STRING in the NON_POWERPC mask.   This is reported incorrectly to
the user as an improper combination of power and powerpc64 options.

Fixing this causes other failures.  These are fixed by the additions to
rs6000.md and rs6000.c

--
Tom Rix
GCC Engineer
trix@redhat.com

2001-12-08  Tom Rix  <trix@redhat.com>

	* config/rs6000/aix43.h (NON_POWERPC_MASKS): Delete MASK_STRING.
	* config/rs6000/aix51.h (NON_POWERPC_MASKS): Same.
 	* config/rs6000/rs6000.md (load_multiple, store_multiple): Do not use 
 	for powerpc64.
 	* config/rs6000/rs6000.md (movstrsi_8reg, movstrsi_6reg, 
 	movstrsi_4reg, movstrsi_1_reg): Add powerpc64.
	* config/rs6000/rs6000.c (expand_block_move): Do not use 
	gen_movstrsi_2reg and powerpc64.

diff -rc gcc-old/config/rs6000/aix43.h gcc/config/rs6000/aix43.h
*** gcc-old/config/rs6000/aix43.h	Fri Dec  7 08:28:52 2001
--- gcc/config/rs6000/aix43.h	Fri Dec  7 21:58:08 2001
***************
*** 40,46 ****
     The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
     get control.  */
  
! #define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
  #define SUBTARGET_OVERRIDE_OPTIONS					\
  do {									\
    if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
--- 40,46 ----
     The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
     get control.  */
  
! #define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
  #define SUBTARGET_OVERRIDE_OPTIONS					\
  do {									\
    if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
diff -rc gcc-old/config/rs6000/aix51.h gcc/config/rs6000/aix51.h
*** gcc-old/config/rs6000/aix51.h	Fri Dec  7 08:28:52 2001
--- gcc/config/rs6000/aix51.h	Fri Dec  7 21:59:32 2001
***************
*** 40,46 ****
     The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
     get control.  */
  
! #define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
  #define SUBTARGET_OVERRIDE_OPTIONS					\
  do {									\
    if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
--- 40,46 ----
     The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
     get control.  */
  
! #define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
  #define SUBTARGET_OVERRIDE_OPTIONS					\
  do {									\
    if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
diff -rc gcc-old/config/rs6000/rs6000.c gcc/config/rs6000/rs6000.c
*** gcc-old/config/rs6000/rs6000.c	Fri Dec  7 08:28:52 2001
--- gcc/config/rs6000/rs6000.c	Sat Dec  8 13:00:41 2001
***************
*** 4064,4070 ****
  						     dest_reg, orig_dest),
  			      tmp_reg);
  	    }
! 	  else if (bytes > 4)
  	    {			/* move up to 8 bytes at a time */
  	      move_bytes = (bytes > 8) ? 8 : bytes;
  	      emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
--- 4064,4070 ----
  						     dest_reg, orig_dest),
  			      tmp_reg);
  	    }
! 	  else if (bytes > 4 && !TARGET_POWERPC64)
  	    {			/* move up to 8 bytes at a time */
  	      move_bytes = (bytes > 8) ? 8 : bytes;
  	      emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
diff -rc gcc-old/config/rs6000/rs6000.md gcc/config/rs6000/rs6000.md
*** gcc-old/config/rs6000/rs6000.md	Fri Dec  7 08:28:53 2001
--- gcc/config/rs6000/rs6000.md	Fri Dec  7 22:14:14 2001
***************
*** 8483,8489 ****
    [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
  			  (match_operand:SI 1 "" ""))
  		     (use (match_operand:SI 2 "" ""))])]
!   "TARGET_STRING"
    "
  {
    int regno;
--- 8483,8489 ----
    [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
  			  (match_operand:SI 1 "" ""))
  		     (use (match_operand:SI 2 "" ""))])]
!   "TARGET_STRING && !TARGET_POWERPC64"
    "
  {
    int regno;
***************
*** 8579,8585 ****
  			  (match_operand:SI 1 "" ""))
  		     (clobber (scratch:SI))
  		     (use (match_operand:SI 2 "" ""))])]
!   "TARGET_STRING"
    "
  {
    int regno;
--- 8579,8585 ----
  			  (match_operand:SI 1 "" ""))
  		     (clobber (scratch:SI))
  		     (use (match_operand:SI 2 "" ""))])]
!   "TARGET_STRING && !TARGET_POWERPC64"
    "
  {
    int regno;
***************
*** 8725,8730 ****
--- 8725,8754 ----
    [(set_attr "type" "load")
     (set_attr "length" "8")])
  
+ (define_insn ""
+   [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
+ 	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
+    (use (match_operand:SI 2 "immediate_operand" "i"))
+    (use (match_operand:SI 3 "immediate_operand" "i"))
+    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
+    (clobber (reg:SI  6))
+    (clobber (reg:SI  7))
+    (clobber (reg:SI  8))
+    (clobber (reg:SI  9))
+    (clobber (reg:SI 10))
+    (clobber (reg:SI 11))
+    (clobber (reg:SI 12))
+    (clobber (match_scratch:SI 5 "X"))]
+   "TARGET_STRING && TARGET_POWERPC64
+    && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
+        || INTVAL (operands[2]) == 0)
+    && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
+    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
+    && REGNO (operands[4]) == 5"
+   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+   [(set_attr "type" "load")
+    (set_attr "length" "8")])
+ 
  ;; Move up to 24 bytes at a time.  The fixed registers are needed because the
  ;; register allocator doesn't have a clue about allocating 6 word registers.
  ;; rD/rS = r5 is preferred, efficient form.
***************
*** 8785,8790 ****
--- 8809,8835 ----
    [(set_attr "type" "load")
     (set_attr "length" "8")])
  
+ (define_insn ""
+   [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
+ 	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
+    (use (match_operand:SI 2 "immediate_operand" "i"))
+    (use (match_operand:SI 3 "immediate_operand" "i"))
+    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
+    (clobber (reg:SI  6))
+    (clobber (reg:SI  7))
+    (clobber (reg:SI  8))
+    (clobber (reg:SI  9))
+    (clobber (reg:SI 10))
+    (clobber (match_scratch:SI 5 "X"))]
+   "TARGET_STRING && TARGET_POWERPC64
+    && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
+    && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
+    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
+    && REGNO (operands[4]) == 5"
+   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+   [(set_attr "type" "load")
+    (set_attr "length" "8")])
+ 
  ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
  ;; problems with TImode.
  ;; rD/rS = r5 is preferred, efficient form.
***************
*** 8839,8844 ****
--- 8884,8908 ----
    [(set_attr "type" "load")
     (set_attr "length" "8")])
  
+ (define_insn ""
+   [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
+ 	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
+    (use (match_operand:SI 2 "immediate_operand" "i"))
+    (use (match_operand:SI 3 "immediate_operand" "i"))
+    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
+    (clobber (reg:SI 6))
+    (clobber (reg:SI 7))
+    (clobber (reg:SI 8))
+    (clobber (match_scratch:SI 5 "X"))]
+   "TARGET_STRING && TARGET_POWERPC64
+    && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
+    && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
+    && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
+    && REGNO (operands[4]) == 5"
+   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+   [(set_attr "type" "load")
+    (set_attr "length" "8")])
+ 
  ;; Move up to 8 bytes at a time.
  (define_expand "movstrsi_2reg"
    [(parallel [(set (match_operand 0 "" "")
***************
*** 8908,8913 ****
--- 8972,8990 ----
     (clobber (match_scratch:SI 4 "=&r"))
     (clobber (match_scratch:SI 5 "X"))]
    "TARGET_STRING && ! TARGET_POWER
+    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
+   [(set_attr "type" "load")
+    (set_attr "length" "8")])
+ 
+ (define_insn ""
+   [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
+ 	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
+    (use (match_operand:SI 2 "immediate_operand" "i"))
+    (use (match_operand:SI 3 "immediate_operand" "i"))
+    (clobber (match_scratch:SI 4 "=&r"))
+    (clobber (match_scratch:SI 5 "X"))]
+   "TARGET_STRING && TARGET_POWERPC64
     && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
    "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
    [(set_attr "type" "load")

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