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PATCH: powerPC imul2 and imul3


As David Edelsohn suggested, this adds the "imul3" insn type
attribute for multiplication by 8 bit constant, in addition
to the "imul2" type for multiplication by 16 bit constant, and
adds new scheduling times for 750/7400/7450.
Bootstrapped and tested on Darwin.
(As before, the define_attr line may be mangled by the mailer.)

2001-12-04  Dale Johannesen   <dalej@apple.com>

         * config/rs6000/rs6000.md:  add imul2 and imul3 insn
         types for multiplication by 16- and 8-bit constants
           config/rs6000/rs6000.c:  new function s8bit_cint_operand
         added for support of above


Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.141
diff -u -d -b -w -c -3 -p -r1.141 rs6000.md
*** rs6000.md   2001/12/01 01:59:00     1.141
--- rs6000.md   2001/12/06 21:47:42
***************
*** 37,43 ****


   ;; Define an insn type attribute.  This is used in function unit delay
   ;; computations.
! (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,
imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,
fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,
altivec"
     (const_string "integer"))

   ;; Length (in bytes).
--- 37,43 ----


   ;; Define an insn type attribute.  This is used in function unit delay
   ;; computations.
! (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,
imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,
fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,
veccmp,vecperm,vecfloat,altivec"
     (const_string "integer"))

   ;; Length (in bytes).
***************
*** 156,172 ****
     1 1)

   (define_function_unit "iu" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "ppc403"))
     4 4)

   (define_function_unit "iu" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "rios1,ppc601,ppc603"))
     5 5)

   (define_function_unit "iu" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "rs64a"))
     20 14)

--- 156,172 ----
     1 1)

   (define_function_unit "iu" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "ppc403"))
     4 4)

   (define_function_unit "iu" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "rios1,ppc601,ppc603"))
     5 5)

   (define_function_unit "iu" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "rs64a"))
     20 14)

***************
*** 216,222 ****
     1 1)

   (define_function_unit "iu2" 2 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "rios2"))
     2 2)

--- 216,222 ----
     1 1)

   (define_function_unit "iu2" 2 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "rios2"))
     2 2)

***************
*** 226,232 ****
     13 13)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "rios2"))
     2 2)

--- 226,232 ----
     13 13)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "rios2"))
     2 2)

***************
*** 238,244 ****
   ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
   ; Divide latency varies greatly from 2-11, use 6 as average
   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "mpccore"))
     2 1)

--- 238,244 ----
   ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
   ; Divide latency varies greatly from 2-11, use 6 as average
   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "mpccore"))
     2 1)

***************
*** 256,267 ****
     1 1)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "ppc604"))
     4 2)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "ppc620,ppc630"))
     5 3)

--- 256,267 ----
     1 1)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "ppc604"))
     4 2)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "ppc620,ppc630"))
     5 3)

***************
*** 271,277 ****
     5 3)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul")
          (eq_attr "cpu" "ppc604e"))
     2 1)

--- 271,277 ----
     5 3)

   (define_function_unit "imuldiv" 1 0
!   (and (eq_attr "type" "imul,imul2,imul3")
          (eq_attr "cpu" "ppc604e"))
     2 1)

***************
*** 309,314 ****
--- 309,319 ----
     4 4)

   (define_function_unit "imuldiv" 1 0
+   (and (eq_attr "type" "imul2,imul3")
+        (eq_attr "cpu" "ppc7450"))
+   3 1)
+
+ (define_function_unit "imuldiv" 1 0
     (and (eq_attr "type" "idiv")
          (eq_attr "cpu" "ppc7450"))
     23 23)
***************
*** 354,359 ****
--- 359,374 ----
     4 4)

   (define_function_unit "iu2" 2 0
+   (and (eq_attr "type" "imul2")
+        (eq_attr "cpu" "ppc750,ppc7400"))
+   3 2)
+
+ (define_function_unit "iu2" 2 0
+   (and (eq_attr "type" "imul3")
+        (eq_attr "cpu" "ppc750,ppc7400"))
+   2 1)
+
+ (define_function_unit "iu2" 2 0
     (and (eq_attr "type" "idiv")
          (eq_attr "cpu" "ppc750,ppc7400"))
     19 19)
***************
*** 364,369 ****
--- 379,394 ----
     4 4)

   (define_function_unit "imuldiv" 1 0
+   (and (eq_attr "type" "imul2")
+        (eq_attr "cpu" "ppc750,ppc7400"))
+   3 2)
+
+ (define_function_unit "imuldiv" 1 0
+   (and (eq_attr "type" "imul3")
+        (eq_attr "cpu" "ppc750,ppc7400"))
+   2 1)
+
+ (define_function_unit "imuldiv" 1 0
     (and (eq_attr "type" "idiv")
          (eq_attr "cpu" "ppc750,ppc7400"))
     19 19)
***************
*** 2157,2163 ****
     "@
      {muls|mullw} %0,%1,%2
      {muli|mulli} %0,%1,%2"
!    [(set_attr "type" "imul")])

   (define_insn "mulsi3_no_mq"
     [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
--- 2187,2198 ----
     "@
      {muls|mullw} %0,%1,%2
      {muli|mulli} %0,%1,%2"
!    [(set (attr "type")
!       (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
!               (const_string "imul3")
!              (match_operand:SI 2 "short_cint_operand" "")
!               (const_string "imul2")]
!       (const_string "imul")))])

   (define_insn "mulsi3_no_mq"
     [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
***************
*** 2167,2173 ****
     "@
      {muls|mullw} %0,%1,%2
      {muli|mulli} %0,%1,%2"
!    [(set_attr "type" "imul")])

   (define_insn ""
     [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 2202,2213 ----
     "@
      {muls|mullw} %0,%1,%2
      {muli|mulli} %0,%1,%2"
!    [(set (attr "type")
!       (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
!               (const_string "imul3")
!              (match_operand:SI 2 "short_cint_operand" "")
!               (const_string "imul2")]
!       (const_string "imul")))])

   (define_insn ""
     [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")

Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.250
diff -u -d -b -w -c -3 -p -r1.250 rs6000.c
*** rs6000.c    2001/12/03 19:13:35     1.250
--- rs6000.c    2001/12/06 21:50:33
*************** xer_operand (op, mode)
*** 678,683 ****
--- 678,695 ----
     return 0;
   }

+ /* Return 1 if OP is a signed 8-bit constant.  Int multiplication
+    by such constants completes more quickly. */
+
+ int
+ s8bit_cint_operand (op, mode)
+      rtx op;
+      enum machine_mode mode ATTRIBUTE_UNUSED;
+ {
+   return ( GET_CODE (op) == CONST_INT
+         && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
+ }
+
   /* Return 1 if OP is a constant that can fit in a D field.  */

   int


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