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patch: rs6000 specific


This adds some additional patterns for multiply-add instructions.
Bootstrapped and tested on Darwin.  (The !POWERPC variants are
included, analogous to what was already there, but I was unable
to test them.)


2001-12-04  Dale Johannesen   <dalej@apple.com>

         * config/rs6000/rs6000.md:  add more multiply-add patterns


Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.141
diff -u -d -b -w -c -3 -p -r1.141 rs6000.md
*** rs6000.md   2001/12/01 01:59:00     1.141
--- rs6000.md   2001/12/04 18:31:09
***************
*** 4818,4823 ****
--- 4837,4843 ----
     "{fd|fdiv} %0,%1,%2"
     [(set_attr "type" "ddiv")])

+ ;; fmadd: D = (A * B) + C
   (define_insn ""
     [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
         (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
***************
*** 4836,4841 ****
--- 4856,4862 ----
     "{fma|fmadd} %0,%1,%2,%3"
     [(set_attr "type" "dmul")])

+ ;; fmsub 1: D = (A * B) - C
   (define_insn ""
     [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
         (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
***************
*** 4854,4859 ****
--- 4875,4942 ----
     "{fms|fmsub} %0,%1,%2,%3"
     [(set_attr "type" "dmul")])

+ ;; fmsub 2: D = -C + (A * B)
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fmsubs %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fms|fmsub} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fmsub 3: D = - ((-A * B) + C)
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (neg:SF (plus:SF (mult:SF
+                          (neg:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f"))
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                        (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fmsubs %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (neg:SF (plus:SF (mult:SF
+                          (neg:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f"))
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                        (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fms|fmsub} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fmsub 4: D = - (C - (A * B))
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (neg:SF (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+                         (mult:SF
+                               (match_operand:SF 1 "gpc_reg_operand" "%f"
)
+                               (match_operand:SF 2 "gpc_reg_operand" "f")
))))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fmsubs %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (neg:SF (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+                         (mult:SF
+                               (match_operand:SF 1 "gpc_reg_operand" "%f"
)
+                               (match_operand:SF 2 "gpc_reg_operand" "f")
))))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fms|fmsub} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fnmadd 1: D = - (A * B + C)
   (define_insn ""
     [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
         (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f")
***************
*** 4872,4879 ****
--- 4955,5001 ----
     "{fnma|fnmadd} %0,%1,%2,%3"
     [(set_attr "type" "dmul")])

+ ;; fnmadd 2: D = (-A * B) - C
   (define_insn ""
     [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f"))
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fnmadds %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f"))
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fnma|fnmadd} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fnmadd 3: D = - C - (A * B)
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (minus:SF (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))
+                 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fnmadds %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (minus:SF (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))
+                 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fnma|fnmadd} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fnmsub 1: D = - (A * B - C)
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
         (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f")
                                    (match_operand:SF 2 "gpc_reg_operand" 
"f"))
                           (match_operand:SF 3 "gpc_reg_operand" "f"))))]
***************
*** 4890,4895 ****
--- 5012,5074 ----
     "{fnms|fnmsub} %0,%1,%2,%3"
     [(set_attr "type" "dmul")])

+ ;; fnmsub 2: D = C - (A * B)
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+                 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fnmsubs %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+                 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fnms|fnmsub} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fnmsub 3: D = - (-C + (A * B))
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f")
+                                  (match_operand:SF 2 "gpc_reg_operand" 
"f"))
+                        (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"
)))))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fnmsubs %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f")
+                                  (match_operand:SF 2 "gpc_reg_operand" 
"f"))
+                        (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"
)))))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fnms|fnmsub} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
+ ;; fnmsub 4: D = (- A * B) + C
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f"))
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                (match_operand:SF 3 "gpc_reg_operand" "f")))]
+   "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "fnmsubs %0,%1,%2,%3"
+   [(set_attr "type" "fp")])
+
+ (define_insn ""
+   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" 
"%f"))
+                          (match_operand:SF 2 "gpc_reg_operand" "f"))
+                (match_operand:SF 3 "gpc_reg_operand" "f")))]
+   "!TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+   "{fnms|fnmsub} %0,%1,%2,%3"
+   [(set_attr "type" "dmul")])
+
   (define_expand "sqrtsf2"
     [(set (match_operand:SF 0 "gpc_reg_operand" "")
         (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]


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