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patch: altivec change tabs to spaces
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: gcc patches <gcc-patches at gcc dot gnu dot org>
- Date: 15 Nov 2001 09:56:11 -0500
- Subject: patch: altivec change tabs to spaces
david pointed out the ppc port uses spaces, not tabs for the output
templates.
i fixed all the altivec patterns. committed as obvious.
2001-11-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md: Use spaces instead of tabs in output
templates.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.131
diff -c -p -r1.131 rs6000.md
*** rs6000.md 2001/11/15 05:21:07 1.131
--- rs6000.md 2001/11/15 14:49:23
***************
*** 13369,13375 ****
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
! "lvx\t%0,%y1"
[(set_attr "type" "altivec")])
;; Generic STVX store instruction.
--- 13369,13375 ----
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
! "lvx %0,%y1"
[(set_attr "type" "altivec")])
;; Generic STVX store instruction.
***************
*** 13377,13383 ****
[(set (match_operand:V4SI 0 "memory_operand" "=m")
(match_operand:V4SI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
! "stvx\t%1,%y0"
[(set_attr "type" "altivec")])
;; Vector move instructions.
--- 13377,13383 ----
[(set (match_operand:V4SI 0 "memory_operand" "=m")
(match_operand:V4SI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
! "stvx %1,%y0"
[(set_attr "type" "altivec")])
;; Vector move instructions.
***************
*** 13392,13400 ****
(match_operand:V4SI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx\t%1,%y0
! ldvx\t%0,%y1
! vor\t%0,%1,%1"
[(set_attr "type" "altivec")])
(define_expand "movv8hi"
--- 13392,13400 ----
(match_operand:V4SI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx %1,%y0
! ldvx %0,%y1
! vor %0,%1,%1"
[(set_attr "type" "altivec")])
(define_expand "movv8hi"
***************
*** 13408,13416 ****
(match_operand:V8HI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx\t%1,%y0
! ldvx\t%0,%y1
! vor\t%0,%1,%1"
[(set_attr "type" "altivec")])
(define_expand "movv16qi"
--- 13408,13416 ----
(match_operand:V8HI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx %1,%y0
! ldvx %0,%y1
! vor %0,%1,%1"
[(set_attr "type" "altivec")])
(define_expand "movv16qi"
***************
*** 13424,13432 ****
(match_operand:V16QI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx\t%1,%y0
! ldvx\t%0,%y1
! vor\t%0,%1,%1"
[(set_attr "type" "altivec")])
(define_expand "movv4sf"
--- 13424,13432 ----
(match_operand:V16QI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx %1,%y0
! ldvx %0,%y1
! vor %0,%1,%1"
[(set_attr "type" "altivec")])
(define_expand "movv4sf"
***************
*** 13440,13448 ****
(match_operand:V4SF 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx\t%1,%y0
! ldvx\t%0,%y1
! vor\t%0,%1,%1"
[(set_attr "type" "altivec")])
;; Simple binary operations.
--- 13440,13448 ----
(match_operand:V4SF 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
! stvx %1,%y0
! ldvx %0,%y1
! vor %0,%1,%1"
[(set_attr "type" "altivec")])
;; Simple binary operations.
***************
*** 13452,13458 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 31))]
"TARGET_ALTIVEC"
! "vaddubm\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduhm"
--- 13452,13458 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 31))]
"TARGET_ALTIVEC"
! "vaddubm %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduhm"
***************
*** 13460,13466 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 32))]
"TARGET_ALTIVEC"
! "vadduhm\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduwm"
--- 13460,13466 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 32))]
"TARGET_ALTIVEC"
! "vadduhm %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduwm"
***************
*** 13468,13474 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 33))]
"TARGET_ALTIVEC"
! "vadduwm\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddfp"
--- 13468,13474 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 33))]
"TARGET_ALTIVEC"
! "vadduwm %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddfp"
***************
*** 13476,13482 ****
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 34))]
"TARGET_ALTIVEC"
! "vaddfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddcuw"
--- 13476,13482 ----
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 34))]
"TARGET_ALTIVEC"
! "vaddfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddcuw"
***************
*** 13484,13490 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 35))]
"TARGET_ALTIVEC"
! "vaddcuw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddubs"
--- 13484,13490 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 35))]
"TARGET_ALTIVEC"
! "vaddcuw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddubs"
***************
*** 13492,13498 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 36))]
"TARGET_ALTIVEC"
! "vaddubs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddsbs"
--- 13492,13498 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 36))]
"TARGET_ALTIVEC"
! "vaddubs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddsbs"
***************
*** 13500,13506 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 37))]
"TARGET_ALTIVEC"
! "vaddsbs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduhs"
--- 13500,13506 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 37))]
"TARGET_ALTIVEC"
! "vaddsbs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduhs"
***************
*** 13508,13514 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 38))]
"TARGET_ALTIVEC"
! "vadduhs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddshs"
--- 13508,13514 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 38))]
"TARGET_ALTIVEC"
! "vadduhs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddshs"
***************
*** 13516,13522 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 39))]
"TARGET_ALTIVEC"
! "vaddshs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduws"
--- 13516,13522 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 39))]
"TARGET_ALTIVEC"
! "vaddshs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vadduws"
***************
*** 13524,13530 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 40))]
"TARGET_ALTIVEC"
! "vadduws\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddsws"
--- 13524,13530 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 40))]
"TARGET_ALTIVEC"
! "vadduws %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vaddsws"
***************
*** 13532,13538 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 41))]
"TARGET_ALTIVEC"
! "vaddsws\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vand"
--- 13532,13538 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 41))]
"TARGET_ALTIVEC"
! "vaddsws %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vand"
***************
*** 13540,13546 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 42))]
"TARGET_ALTIVEC"
! "vand\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vandc"
--- 13540,13546 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 42))]
"TARGET_ALTIVEC"
! "vand %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vandc"
***************
*** 13548,13554 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 43))]
"TARGET_ALTIVEC"
! "vandc\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgub"
--- 13548,13554 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 43))]
"TARGET_ALTIVEC"
! "vandc %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgub"
***************
*** 13556,13562 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 44))]
"TARGET_ALTIVEC"
! "vavgub\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgsb"
--- 13556,13562 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 44))]
"TARGET_ALTIVEC"
! "vavgub %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgsb"
***************
*** 13564,13570 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 45))]
"TARGET_ALTIVEC"
! "vavgsb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavguh"
--- 13564,13570 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 45))]
"TARGET_ALTIVEC"
! "vavgsb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavguh"
***************
*** 13572,13578 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 46))]
"TARGET_ALTIVEC"
! "vavguh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgsh"
--- 13572,13578 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 46))]
"TARGET_ALTIVEC"
! "vavguh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgsh"
***************
*** 13580,13586 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 47))]
"TARGET_ALTIVEC"
! "vavgsh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavguw"
--- 13580,13586 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 47))]
"TARGET_ALTIVEC"
! "vavgsh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavguw"
***************
*** 13588,13594 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 48))]
"TARGET_ALTIVEC"
! "vavguw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgsw"
--- 13588,13594 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 48))]
"TARGET_ALTIVEC"
! "vavguw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vavgsw"
***************
*** 13596,13602 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 49))]
"TARGET_ALTIVEC"
! "vavgsw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpbfp"
--- 13596,13602 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 49))]
"TARGET_ALTIVEC"
! "vavgsw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpbfp"
***************
*** 13604,13610 ****
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 50))]
"TARGET_ALTIVEC"
! "vcmpbfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequb"
--- 13604,13610 ----
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 50))]
"TARGET_ALTIVEC"
! "vcmpbfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequb"
***************
*** 13612,13618 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 51))]
"TARGET_ALTIVEC"
! "vcmpequb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequh"
--- 13612,13618 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 51))]
"TARGET_ALTIVEC"
! "vcmpequb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequh"
***************
*** 13620,13626 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 52))]
"TARGET_ALTIVEC"
! "vcmpequh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequw"
--- 13620,13626 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 52))]
"TARGET_ALTIVEC"
! "vcmpequh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequw"
***************
*** 13628,13634 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 53))]
"TARGET_ALTIVEC"
! "vcmpequw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpeqfp"
--- 13628,13634 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 53))]
"TARGET_ALTIVEC"
! "vcmpequw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpeqfp"
***************
*** 13636,13642 ****
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 54))]
"TARGET_ALTIVEC"
! "vcmpeqfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgefp"
--- 13636,13642 ----
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 54))]
"TARGET_ALTIVEC"
! "vcmpeqfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgefp"
***************
*** 13644,13650 ****
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 55))]
"TARGET_ALTIVEC"
! "vcmpgefp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtub"
--- 13644,13650 ----
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 55))]
"TARGET_ALTIVEC"
! "vcmpgefp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtub"
***************
*** 13652,13658 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 56))]
"TARGET_ALTIVEC"
! "vcmpgtub\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsb"
--- 13652,13658 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 56))]
"TARGET_ALTIVEC"
! "vcmpgtub %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsb"
***************
*** 13660,13666 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 57))]
"TARGET_ALTIVEC"
! "vcmpgtsb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuh"
--- 13660,13666 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 57))]
"TARGET_ALTIVEC"
! "vcmpgtsb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuh"
***************
*** 13668,13674 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 58))]
"TARGET_ALTIVEC"
! "vcmpgtuh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsh"
--- 13668,13674 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 58))]
"TARGET_ALTIVEC"
! "vcmpgtuh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsh"
***************
*** 13676,13682 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 59))]
"TARGET_ALTIVEC"
! "vcmpgtsh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuw"
--- 13676,13682 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 59))]
"TARGET_ALTIVEC"
! "vcmpgtsh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuw"
***************
*** 13684,13690 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 60))]
"TARGET_ALTIVEC"
! "vcmpgtuw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsw"
--- 13684,13690 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 60))]
"TARGET_ALTIVEC"
! "vcmpgtuw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsw"
***************
*** 13692,13698 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 61))]
"TARGET_ALTIVEC"
! "vcmpgtsw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtfp"
--- 13692,13698 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 61))]
"TARGET_ALTIVEC"
! "vcmpgtsw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtfp"
***************
*** 13700,13706 ****
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 62))]
"TARGET_ALTIVEC"
! "vcmpgtfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxub"
--- 13700,13706 ----
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 62))]
"TARGET_ALTIVEC"
! "vcmpgtfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxub"
***************
*** 13708,13714 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 63))]
"TARGET_ALTIVEC"
! "vmaxub\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsb"
--- 13708,13714 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 63))]
"TARGET_ALTIVEC"
! "vmaxub %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsb"
***************
*** 13716,13722 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 64))]
"TARGET_ALTIVEC"
! "vmaxsb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxuh"
--- 13716,13722 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 64))]
"TARGET_ALTIVEC"
! "vmaxsb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxuh"
***************
*** 13724,13730 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 65))]
"TARGET_ALTIVEC"
! "vmaxuh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsh"
--- 13724,13730 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 65))]
"TARGET_ALTIVEC"
! "vmaxuh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsh"
***************
*** 13732,13738 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 66))]
"TARGET_ALTIVEC"
! "vmaxsh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxuw"
--- 13732,13738 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 66))]
"TARGET_ALTIVEC"
! "vmaxsh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxuw"
***************
*** 13740,13746 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 67))]
"TARGET_ALTIVEC"
! "vmaxuw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsw"
--- 13740,13746 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 67))]
"TARGET_ALTIVEC"
! "vmaxuw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxsw"
***************
*** 13748,13754 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 68))]
"TARGET_ALTIVEC"
! "vmaxsw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxfp"
--- 13748,13754 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 68))]
"TARGET_ALTIVEC"
! "vmaxsw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmaxfp"
***************
*** 13756,13762 ****
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 69))]
"TARGET_ALTIVEC"
! "vmaxfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrghb"
--- 13756,13762 ----
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 69))]
"TARGET_ALTIVEC"
! "vmaxfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrghb"
***************
*** 13764,13770 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 70))]
"TARGET_ALTIVEC"
! "vmrghb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrghh"
--- 13764,13770 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 70))]
"TARGET_ALTIVEC"
! "vmrghb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrghh"
***************
*** 13772,13778 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 71))]
"TARGET_ALTIVEC"
! "vmrghh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrghw"
--- 13772,13778 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 71))]
"TARGET_ALTIVEC"
! "vmrghh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrghw"
***************
*** 13780,13786 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 72))]
"TARGET_ALTIVEC"
! "vmrghw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrglb"
--- 13780,13786 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 72))]
"TARGET_ALTIVEC"
! "vmrghw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrglb"
***************
*** 13788,13794 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 73))]
"TARGET_ALTIVEC"
! "vmrglb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrglh"
--- 13788,13794 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 73))]
"TARGET_ALTIVEC"
! "vmrglb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrglh"
***************
*** 13796,13802 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 74))]
"TARGET_ALTIVEC"
! "vmrglh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrglw"
--- 13796,13802 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 74))]
"TARGET_ALTIVEC"
! "vmrglh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmrglw"
***************
*** 13804,13810 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 75))]
"TARGET_ALTIVEC"
! "vmrglw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminub"
--- 13804,13810 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 75))]
"TARGET_ALTIVEC"
! "vmrglw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminub"
***************
*** 13812,13818 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 76))]
"TARGET_ALTIVEC"
! "vminub\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminsb"
--- 13812,13818 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 76))]
"TARGET_ALTIVEC"
! "vminub %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminsb"
***************
*** 13820,13826 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 77))]
"TARGET_ALTIVEC"
! "vminsb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminuh"
--- 13820,13826 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 77))]
"TARGET_ALTIVEC"
! "vminsb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminuh"
***************
*** 13828,13834 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 78))]
"TARGET_ALTIVEC"
! "vminuh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminsh"
--- 13828,13834 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 78))]
"TARGET_ALTIVEC"
! "vminuh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminsh"
***************
*** 13836,13842 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 79))]
"TARGET_ALTIVEC"
! "vminsh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminuw"
--- 13836,13842 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 79))]
"TARGET_ALTIVEC"
! "vminsh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminuw"
***************
*** 13844,13850 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 80))]
"TARGET_ALTIVEC"
! "vminuw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminsw"
--- 13844,13850 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 80))]
"TARGET_ALTIVEC"
! "vminuw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminsw"
***************
*** 13852,13858 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 81))]
"TARGET_ALTIVEC"
! "vminsw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminfp"
--- 13852,13858 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 81))]
"TARGET_ALTIVEC"
! "vminsw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vminfp"
***************
*** 13860,13866 ****
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 82))]
"TARGET_ALTIVEC"
! "vminfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmuleub"
--- 13860,13866 ----
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 82))]
"TARGET_ALTIVEC"
! "vminfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmuleub"
***************
*** 13868,13874 ****
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 83))]
"TARGET_ALTIVEC"
! "vmuleub\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulesb"
--- 13868,13874 ----
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 83))]
"TARGET_ALTIVEC"
! "vmuleub %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulesb"
***************
*** 13876,13882 ****
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 84))]
"TARGET_ALTIVEC"
! "vmulesb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmuleuh"
--- 13876,13882 ----
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 84))]
"TARGET_ALTIVEC"
! "vmulesb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmuleuh"
***************
*** 13884,13890 ****
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 85))]
"TARGET_ALTIVEC"
! "vmuleuh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulesh"
--- 13884,13890 ----
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 85))]
"TARGET_ALTIVEC"
! "vmuleuh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulesh"
***************
*** 13892,13898 ****
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 86))]
"TARGET_ALTIVEC"
! "vmulesh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmuloub"
--- 13892,13898 ----
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 86))]
"TARGET_ALTIVEC"
! "vmulesh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmuloub"
***************
*** 13900,13906 ****
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 87))]
"TARGET_ALTIVEC"
! "vmuloub\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulosb"
--- 13900,13906 ----
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 87))]
"TARGET_ALTIVEC"
! "vmuloub %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulosb"
***************
*** 13908,13914 ****
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 88))]
"TARGET_ALTIVEC"
! "vmulosb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulouh"
--- 13908,13914 ----
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 88))]
"TARGET_ALTIVEC"
! "vmulosb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulouh"
***************
*** 13916,13922 ****
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 89))]
"TARGET_ALTIVEC"
! "vmulouh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulosh"
--- 13916,13922 ----
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 89))]
"TARGET_ALTIVEC"
! "vmulouh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vmulosh"
***************
*** 13924,13930 ****
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 90))]
"TARGET_ALTIVEC"
! "vmulosh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vnor"
--- 13924,13930 ----
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 90))]
"TARGET_ALTIVEC"
! "vmulosh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vnor"
***************
*** 13932,13938 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 91))]
"TARGET_ALTIVEC"
! "vnor\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vor"
--- 13932,13938 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 91))]
"TARGET_ALTIVEC"
! "vnor %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vor"
***************
*** 13940,13946 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 92))]
"TARGET_ALTIVEC"
! "vor\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhum"
--- 13940,13946 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 92))]
"TARGET_ALTIVEC"
! "vor %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhum"
***************
*** 13948,13954 ****
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 93))]
"TARGET_ALTIVEC"
! "vpkuhum\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwum"
--- 13948,13954 ----
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 93))]
"TARGET_ALTIVEC"
! "vpkuhum %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwum"
***************
*** 13956,13962 ****
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 94))]
"TARGET_ALTIVEC"
! "vpkuwum\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkpx"
--- 13956,13962 ----
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 94))]
"TARGET_ALTIVEC"
! "vpkuwum %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkpx"
***************
*** 13964,13970 ****
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 95))]
"TARGET_ALTIVEC"
! "vpkpx\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhss"
--- 13964,13970 ----
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 95))]
"TARGET_ALTIVEC"
! "vpkpx %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhss"
***************
*** 13972,13978 ****
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 96))]
"TARGET_ALTIVEC"
! "vpkuhss\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkshss"
--- 13972,13978 ----
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 96))]
"TARGET_ALTIVEC"
! "vpkuhss %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkshss"
***************
*** 13980,13986 ****
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 97))]
"TARGET_ALTIVEC"
! "vpkshss\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwss"
--- 13980,13986 ----
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 97))]
"TARGET_ALTIVEC"
! "vpkshss %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwss"
***************
*** 13988,13994 ****
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 98))]
"TARGET_ALTIVEC"
! "vpkuwss\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkswss"
--- 13988,13994 ----
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 98))]
"TARGET_ALTIVEC"
! "vpkuwss %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkswss"
***************
*** 13996,14002 ****
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 99))]
"TARGET_ALTIVEC"
! "vpkswss\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhus"
--- 13996,14002 ----
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 99))]
"TARGET_ALTIVEC"
! "vpkswss %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhus"
***************
*** 14004,14010 ****
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 100))]
"TARGET_ALTIVEC"
! "vpkuhus\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkshus"
--- 14004,14010 ----
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 100))]
"TARGET_ALTIVEC"
! "vpkuhus %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkshus"
***************
*** 14012,14018 ****
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 101))]
"TARGET_ALTIVEC"
! "vpkshus\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwus"
--- 14012,14018 ----
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 101))]
"TARGET_ALTIVEC"
! "vpkshus %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwus"
***************
*** 14020,14026 ****
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 102))]
"TARGET_ALTIVEC"
! "vpkuwus\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkswus"
--- 14020,14026 ----
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 102))]
"TARGET_ALTIVEC"
! "vpkuwus %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vpkswus"
***************
*** 14028,14034 ****
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 103))]
"TARGET_ALTIVEC"
! "vpkswus\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrlb"
--- 14028,14034 ----
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 103))]
"TARGET_ALTIVEC"
! "vpkswus %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrlb"
***************
*** 14036,14042 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 104))]
"TARGET_ALTIVEC"
! "vrlb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrlh"
--- 14036,14042 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 104))]
"TARGET_ALTIVEC"
! "vrlb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrlh"
***************
*** 14044,14050 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 105))]
"TARGET_ALTIVEC"
! "vrlh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrlw"
--- 14044,14050 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 105))]
"TARGET_ALTIVEC"
! "vrlh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrlw"
***************
*** 14052,14058 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 106))]
"TARGET_ALTIVEC"
! "vrlw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslb"
--- 14052,14058 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 106))]
"TARGET_ALTIVEC"
! "vrlw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslb"
***************
*** 14060,14066 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 107))]
"TARGET_ALTIVEC"
! "vslb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslh"
--- 14060,14066 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 107))]
"TARGET_ALTIVEC"
! "vslb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslh"
***************
*** 14068,14074 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 108))]
"TARGET_ALTIVEC"
! "vslh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslw"
--- 14068,14074 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 108))]
"TARGET_ALTIVEC"
! "vslh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslw"
***************
*** 14076,14082 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 109))]
"TARGET_ALTIVEC"
! "vslw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsl"
--- 14076,14082 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 109))]
"TARGET_ALTIVEC"
! "vslw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsl"
***************
*** 14084,14090 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 110))]
"TARGET_ALTIVEC"
! "vsl\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslo"
--- 14084,14090 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 110))]
"TARGET_ALTIVEC"
! "vsl %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vslo"
***************
*** 14092,14098 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 111))]
"TARGET_ALTIVEC"
! "vslo\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsrb"
--- 14092,14098 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 111))]
"TARGET_ALTIVEC"
! "vslo %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsrb"
***************
*** 14100,14106 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC"
! "vsrb\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrsh"
--- 14100,14106 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC"
! "vsrb %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrsh"
***************
*** 14108,14114 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 113))]
"TARGET_ALTIVEC"
! "vrsh\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrsw"
--- 14108,14114 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 113))]
"TARGET_ALTIVEC"
! "vrsh %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vrsw"
***************
*** 14116,14122 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 114))]
"TARGET_ALTIVEC"
! "vrsw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsrab"
--- 14116,14122 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 114))]
"TARGET_ALTIVEC"
! "vrsw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsrab"
***************
*** 14124,14130 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC"
! "vsrab\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsrah"
--- 14124,14130 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC"
! "vsrab %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsrah"
***************
*** 14132,14138 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 116))]
"TARGET_ALTIVEC"
! "vsrah\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsraw"
--- 14132,14138 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 116))]
"TARGET_ALTIVEC"
! "vsrah %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsraw"
***************
*** 14140,14146 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 117))]
"TARGET_ALTIVEC"
! "vsraw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsr"
--- 14140,14146 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 117))]
"TARGET_ALTIVEC"
! "vsraw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsr"
***************
*** 14148,14154 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 118))]
"TARGET_ALTIVEC"
! "vsr\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsro"
--- 14148,14154 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 118))]
"TARGET_ALTIVEC"
! "vsr %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsro"
***************
*** 14156,14162 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 119))]
"TARGET_ALTIVEC"
! "vsro\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsububm"
--- 14156,14162 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 119))]
"TARGET_ALTIVEC"
! "vsro %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsububm"
***************
*** 14164,14170 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 120))]
"TARGET_ALTIVEC"
! "vsububm\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhm"
--- 14164,14170 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 120))]
"TARGET_ALTIVEC"
! "vsububm %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhm"
***************
*** 14172,14178 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 121))]
"TARGET_ALTIVEC"
! "vsubuhm\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuwm"
--- 14172,14178 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 121))]
"TARGET_ALTIVEC"
! "vsubuhm %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuwm"
***************
*** 14180,14186 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 122))]
"TARGET_ALTIVEC"
! "vsubuwm\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubfp"
--- 14180,14186 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 122))]
"TARGET_ALTIVEC"
! "vsubuwm %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubfp"
***************
*** 14188,14194 ****
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 123))]
"TARGET_ALTIVEC"
! "vsubfp\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubcuw"
--- 14188,14194 ----
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 123))]
"TARGET_ALTIVEC"
! "vsubfp %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubcuw"
***************
*** 14196,14202 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 124))]
"TARGET_ALTIVEC"
! "vsubcuw\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsububs"
--- 14196,14202 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 124))]
"TARGET_ALTIVEC"
! "vsubcuw %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsububs"
***************
*** 14204,14210 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 125))]
"TARGET_ALTIVEC"
! "vsububs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubsbs"
--- 14204,14210 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 125))]
"TARGET_ALTIVEC"
! "vsububs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubsbs"
***************
*** 14212,14218 ****
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 126))]
"TARGET_ALTIVEC"
! "vsubsbs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhs"
--- 14212,14218 ----
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 126))]
"TARGET_ALTIVEC"
! "vsubsbs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhs"
***************
*** 14220,14226 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 127))]
"TARGET_ALTIVEC"
! "vsubuhs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubshs"
--- 14220,14226 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 127))]
"TARGET_ALTIVEC"
! "vsubuhs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubshs"
***************
*** 14228,14234 ****
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 128))]
"TARGET_ALTIVEC"
! "vsubshs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuws"
--- 14228,14234 ----
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 128))]
"TARGET_ALTIVEC"
! "vsubshs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubuws"
***************
*** 14236,14242 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 129))]
"TARGET_ALTIVEC"
! "vsubuws\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubsws"
--- 14236,14242 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 129))]
"TARGET_ALTIVEC"
! "vsubuws %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsubsws"
***************
*** 14244,14250 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 130))]
"TARGET_ALTIVEC"
! "vsubsws\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum4ubs"
--- 14244,14250 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 130))]
"TARGET_ALTIVEC"
! "vsubsws %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum4ubs"
***************
*** 14252,14258 ****
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 131))]
"TARGET_ALTIVEC"
! "vsum4ubs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum4sbs"
--- 14252,14258 ----
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 131))]
"TARGET_ALTIVEC"
! "vsum4ubs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum4sbs"
***************
*** 14260,14266 ****
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 132))]
"TARGET_ALTIVEC"
! "vsum4sbs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum4shs"
--- 14260,14266 ----
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 132))]
"TARGET_ALTIVEC"
! "vsum4sbs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum4shs"
***************
*** 14268,14274 ****
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 133))]
"TARGET_ALTIVEC"
! "vsum4shs\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum2sws"
--- 14268,14274 ----
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 133))]
"TARGET_ALTIVEC"
! "vsum4shs %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsum2sws"
***************
*** 14276,14282 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 134))]
"TARGET_ALTIVEC"
! "vsum2sws\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsumsws"
--- 14276,14282 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 134))]
"TARGET_ALTIVEC"
! "vsum2sws %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vsumsws"
***************
*** 14284,14290 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 135))]
"TARGET_ALTIVEC"
! "vsumsws\t%0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vxor"
--- 14284,14290 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 135))]
"TARGET_ALTIVEC"
! "vsumsws %0,%1,%2"
[(set_attr "type" "altivec")])
(define_insn "altivec_vxor"
***************
*** 14292,14296 ****
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 136))]
"TARGET_ALTIVEC"
! "vxor\t%0,%1,%2"
[(set_attr "type" "altivec")])
--- 14292,14296 ----
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 136))]
"TARGET_ALTIVEC"
! "vxor %0,%1,%2"
[(set_attr "type" "altivec")])