[patch] mips _flush_cache options

[DJ Delorie <dj at redhat dot com>]

A while ago I wrote this:

> GCC unconditionally expects the OS to have _flush_cache() equivalent
> for trampolines to work, but has no provisions for cases where there
> is no _flush_cache() available.
> 
> Which of the following makes the most sense as a solution?
> 
> 1. All MIPS targets must have a suitable function that takes the right
>    arguments, and #define CACHE_FLUSH_FUNC appropriately.
> 
> 2. Add an option to gcc to specify the flush function, or to indicate
>    that there is no such function (and perhaps thus no cache to flush).
> 
> 3. Something else.

I got requests for both 1 and 2, and would have gone with 1 (it's
easier ;) except that it doesn't handle the case where the function
name depends on what board you're targetting.  You shouldn't have to
rebuild gcc just because you're linking against a different library.
Supporting #2 wasn't hard and doesn't preclude #1, so...

2001-10-29  DJ Delorie  <dj@redhat.com>

	* config/mips/mips.h (mips_cache_flush_func): Prototype.
	(TARGET_OPTIONS): Support -mflush-func= and -mno-flush-func.
	(INITIALIZE_TRAMPOLINE): Use mips_cache_flush_func if nonzero.
	* config/mips/mips.c (mips_cache_flush_func): New.
	* doc/invoke.texi: Document the new options.

The only testing this got was hand-building
gcc.c-torture/execute/921215-1.c with various options and inspecting
the output, and "make info dvi".  I can do a make check if needed...

Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.69
diff -p -3 -r1.69 invoke.texi
*** doc/invoke.texi	2001/10/28 19:12:12	1.69
--- doc/invoke.texi	2001/10/30 04:59:50
*************** in the following sections.
*** 462,468 ****
  -m4650  -msingle-float  -mmad @gol
  -mstats  -EL  -EB  -G @var{num}  -nocpp @gol
  -mabi=32  -mabi=n32  -mabi=64  -mabi=eabi @gol
! -mfix7000  -mno-crt0}
  
  @emph{i386 and x86-64 Options}
  @gccoptlist{
--- 462,468 ----
  -m4650  -msingle-float  -mmad @gol
  -mstats  -EL  -EB  -G @var{num}  -nocpp @gol
  -mabi=32  -mabi=n32  -mabi=64  -mabi=eabi @gol
! -mfix7000  -mno-crt0 -mflush-func=@var{func} -mno-flush-func}
  
  @emph{i386 and x86-64 Options}
  @gccoptlist{
*************** occurs in the following two instructions
*** 7431,7436 ****
--- 7431,7447 ----
  @item -no-crt0
  @opindex no-crt0
  Do not include the default crt0.
+ 
+ @item -mflush-func=@var{func}
+ @itemx -mno-flush-func
+ @opindex mflush-func
+ Specifies the function to call to flush the I and D caches, or to not
+ call any such function.  If called, the function must take the same
+ arguments as the common @code{_flush_func()}, that is, the address of the
+ memory range for which the cache is being flushed, the size of the
+ memory range, and the number 3 (to flush both caches).  The default
+ depends on the target gcc was configured for, but commonly is either
+ @samp{_flush_func} or @samp{__cpu_flush}.
  @end table
  
  @ifset INTERNALS
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.156
diff -p -3 -r1.156 mips.c
*** config/mips/mips.c	2001/10/27 22:41:00	1.156
--- config/mips/mips.c	2001/10/30 05:00:28
*************** int mips16_hard_float;
*** 262,267 ****
--- 262,269 ----
     avoid using up another bit in target_flags.  */
  const char *mips_entry_string;
  
+ const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
+ 
  /* Whether we should entry and exit pseudo-ops in mips16 mode.  */
  int mips_entry;
  
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.136
diff -p -3 -r1.136 mips.h
*** config/mips/mips.h	2001/10/27 22:41:00	1.136
--- config/mips/mips.h	2001/10/30 05:00:54
*************** extern const char *mips_abi_string;	/* f
*** 163,168 ****
--- 163,169 ----
  extern const char *mips_entry_string;	/* for -mentry */
  extern const char *mips_no_mips16_string;/* for -mno-mips16 */
  extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
+ extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
  extern int mips_split_addresses;	/* perform high/lo_sum support */
  extern int dslots_load_total;		/* total # load related delay slots */
  extern int dslots_load_filled;		/* # filled load delay slots */
*************** extern void		sbss_section PARAMS ((void)
*** 625,630 ****
--- 626,635 ----
        N_("Don't use MIPS16 instructions")},				\
    { "explicit-type-size", &mips_explicit_type_size_string,		\
        NULL},								\
+   { "no-flush-func", &mips_cache_flush_func,				\
+       N_("Don't call any cache flush functions")},			\
+   { "flush-func=", &mips_cache_flush_func,				\
+       N_("Specify cache flush function")},				\
  }
  
  /* This is meant to be redefined in the host dependent files.  */
*************** typedef struct mips_args {
*** 2832,2841 ****
    /* Flush both caches.  We need to flush the data cache in case	    \
       the system has a write-back cache.  */				    \
    /* ??? Should check the return value for errors.  */			    \
!   emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC),	    \
! 		     0, VOIDmode, 3, addr, Pmode,			    \
! 		     GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
! 		     GEN_INT (3), TYPE_MODE (integer_type_node));	    \
  }
  
  /* Addressing modes, and classification of registers for them.  */
--- 2837,2847 ----
    /* Flush both caches.  We need to flush the data cache in case	    \
       the system has a write-back cache.  */				    \
    /* ??? Should check the return value for errors.  */			    \
!   if (mips_cache_flush_func && mips_cache_flush_func[0])		    \
!     emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),   \
! 		       0, VOIDmode, 3, addr, Pmode,			    \
! 		       GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
! 		       GEN_INT (3), TYPE_MODE (integer_type_node));	    \
  }
  
  /* Addressing modes, and classification of registers for them.  */