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[PATCH] PowerPC 64-bit addition and division
- To: Geoff Keating <geoffk at redhat dot com>, Mark Mitchell <mark at codesourcery dot com>
- Subject: [PATCH] PowerPC 64-bit addition and division
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Fri, 13 Jul 2001 12:56:17 -0400
- cc: gcc-patches at gcc dot gnu dot org
I would like to apply the following patch on both the trunk and
the gcc-3.0 branch. This patch fixes PR/3464 (GCC generating incorrect
additions of large constants) and another problem that I uncovered while
testing this (GCC incorrectly converting divisions by negative numbers
which appeared positive into shifts: execute/divconst-2.c).
I have tested this on AIX (both 32-bit and 64-bit modes). Daniel
Berlin has tested this on powerpc-linux. No regressions occurred (and
execute/divconst-2.c now passes in AIX 64-bit mode).
The GCC development trunk currently is broken, so I will wait
before committing this to the trunk. Is there any objection to my
committing this to the gcc-3.0 branch?
Thanks, David
2001-07-13 David Edelsohn <edelsohn@gnu.org>
* rs6000.c (reg_or_{add,sub}_cint64_operand): New predicates.
(add_operand): Compare CONST_INT with fewer function calls.
(print_operand, case 'p'): Ensure positive operand.
* rs6000.h (CONST_OK_FOR_LETTER_P, case 'N'): Ensure positive value.
(PREDICATE_CODES): Add new predicates.
* rs6000.md (addsi3): Split 32-bit constants more correctly.
(divsi3, modsi3): Ensure positive power-of-2.
(adddi3): Use new predicate. Split 32-bit constants more
correctly. Re-arrange splitter to handle any constant.
(subdi3): Use new predicate.
(divdi3, moddi3): Ensure positive power-of-2.
Index: rs6000-protos.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000-protos.h,v
retrieving revision 1.16.2.2
diff -c -p -r1.16.2.2 rs6000-protos.h
*** rs6000-protos.h 2001/06/22 02:28:38 1.16.2.2
--- rs6000-protos.h 2001/07/13 16:40:44
*************** extern int reg_or_neg_short_operand PARA
*** 42,47 ****
--- 42,49 ----
extern int reg_or_u_short_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_arith_cint_operand PARAMS ((rtx, enum machine_mode));
+ extern int reg_or_add_cint64_operand PARAMS ((rtx, enum machine_mode));
+ extern int reg_or_sub_cint64_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_logical_cint_operand PARAMS ((rtx, enum machine_mode));
extern int got_operand PARAMS ((rtx, enum machine_mode));
extern int got_no_const_operand PARAMS ((rtx, enum machine_mode));
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.167.2.7
diff -c -p -r1.167.2.7 rs6000.c
*** rs6000.c 2001/06/22 02:28:38 1.167.2.7
--- rs6000.c 2001/07/13 16:40:45
*************** reg_or_arith_cint_operand (op, mode)
*** 679,684 ****
--- 679,720 ----
));
}
+ /* Return 1 is the operand is either a non-special register or a 32-bit
+ signed constant integer valid for 64-bit addition. */
+
+ int
+ reg_or_add_cint64_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+ {
+ return (gpc_reg_operand (op, mode)
+ || (GET_CODE (op) == CONST_INT
+ && INTVAL (op) < 0x7fff8000
+ #if HOST_BITS_PER_WIDE_INT != 32
+ && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
+ < 0x100000000u)
+ #endif
+ ));
+ }
+
+ /* Return 1 is the operand is either a non-special register or a 32-bit
+ signed constant integer valid for 64-bit subtraction. */
+
+ int
+ reg_or_sub_cint64_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+ {
+ return (gpc_reg_operand (op, mode)
+ || (GET_CODE (op) == CONST_INT
+ && (- INTVAL (op)) < 0x7fff8000
+ #if HOST_BITS_PER_WIDE_INT != 32
+ && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
+ < 0x100000000u)
+ #endif
+ ));
+ }
+
/* Return 1 is the operand is either a non-special register or ANY
32-bit unsigned constant integer. */
*************** add_operand (op, mode)
*** 973,981 ****
register rtx op;
enum machine_mode mode;
{
! return (reg_or_short_operand (op, mode)
! || (GET_CODE (op) == CONST_INT
! && CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')));
}
/* Return 1 if OP is a constant but not a valid add_operand. */
--- 1009,1019 ----
register rtx op;
enum machine_mode mode;
{
! if (GET_CODE (op) == CONST_INT)
! return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I')
! || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L'));
!
! return gpc_reg_operand (op, mode);
}
/* Return 1 if OP is a constant but not a valid add_operand. */
*************** print_operand (file, x, code)
*** 4046,4051 ****
--- 4084,4090 ----
case 'p':
/* X is a CONST_INT that is a power of two. Output the logarithm. */
if (! INT_P (x)
+ || INT_LOWPART (x) < 0
|| (i = exact_log2 (INT_LOWPART (x))) < 0)
output_operand_lossage ("invalid %%p value");
else
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.105.2.5
diff -c -p -r1.105.2.5 rs6000.h
*** rs6000.h 2001/06/22 02:28:38 1.105.2.5
--- rs6000.h 2001/07/13 16:40:45
*************** enum reg_class
*** 1044,1050 ****
`K' is a constant with only the low-order 16 bits non-zero
`L' is a signed 16-bit constant shifted left 16 bits
`M' is a constant that is greater than 31
! `N' is a constant that is an exact power of two
`O' is the constant zero
`P' is a constant whose negation is a signed 16-bit constant */
--- 1044,1050 ----
`K' is a constant with only the low-order 16 bits non-zero
`L' is a signed 16-bit constant shifted left 16 bits
`M' is a constant that is greater than 31
! `N' is a positive constant that is an exact power of two
`O' is the constant zero
`P' is a constant whose negation is a signed 16-bit constant */
*************** enum reg_class
*** 1055,1061 ****
: (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
&& ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
: (C) == 'M' ? (VALUE) > 31 \
! : (C) == 'N' ? exact_log2 (VALUE) >= 0 \
: (C) == 'O' ? (VALUE) == 0 \
: (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
: 0)
--- 1055,1061 ----
: (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
&& ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
: (C) == 'M' ? (VALUE) > 31 \
! : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
: (C) == 'O' ? (VALUE) == 0 \
: (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
: 0)
*************** do { \
*** 2675,2680 ****
--- 2675,2682 ----
{"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
+ {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
+ {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.108.4.7
diff -c -p -r1.108.4.7 rs6000.md
*** rs6000.md 2001/06/22 02:28:38 1.108.4.7
--- rs6000.md 2001/07/13 16:40:45
***************
*** 1422,1437 ****
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (SImode));
! HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
! HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
- if (low & 0x8000)
- high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
-
/* The ordering here is important for the prolog expander.
When space is allocated from the stack, adding 'low' first may
produce a temporary deallocation (which would be bad). */
! emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
DONE;
}
--- 1422,1435 ----
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (SImode));
! HOST_WIDE_INT val = INTVAL (operands[2]);
! HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
! HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
/* The ordering here is important for the prolog expander.
When space is allocated from the stack, adding 'low' first may
produce a temporary deallocation (which would be bad). */
! emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
DONE;
}
***************
*** 1525,1537 ****
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
"
{
! HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
! HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
!
! if (low & 0x8000)
! high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
! operands[3] = GEN_INT (high);
operands[4] = GEN_INT (low);
}")
--- 1523,1533 ----
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
"
{
! HOST_WIDE_INT val = INTVAL (operands[2]);
! HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
! HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
! operands[3] = GEN_INT (rest);
operands[4] = GEN_INT (low);
}")
***************
*** 2263,2268 ****
--- 2259,2265 ----
"
{
if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 0
&& exact_log2 (INTVAL (operands[2])) >= 0)
;
else if (TARGET_POWERPC)
***************
*** 2314,2327 ****
rtx temp1;
rtx temp2;
! if (GET_CODE (operands[2]) != CONST_INT)
FAIL;
- i = exact_log2 (INTVAL (operands[2]));
-
- if (i < 0)
- FAIL;
-
temp1 = gen_reg_rtx (SImode);
temp2 = gen_reg_rtx (SImode);
--- 2311,2321 ----
rtx temp1;
rtx temp2;
! if (GET_CODE (operands[2]) != CONST_INT
! || INTVAL (operands[2]) < 0
! || (i = exact_log2 (INTVAL (operands[2]))) < 0)
FAIL;
temp1 = gen_reg_rtx (SImode);
temp2 = gen_reg_rtx (SImode);
***************
*** 2335,2341 ****
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "N")))]
! "exact_log2 (INTVAL (operands[2])) >= 0"
"{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
[(set_attr "length" "8")])
--- 2329,2335 ----
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "N")))]
! "INTVAL (operands[2]) > 0 && exact_log2 (INTVAL (operands[2])) >= 0"
"{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
[(set_attr "length" "8")])
***************
*** 2345,2351 ****
(match_operand:SI 2 "const_int_operand" "N,N"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
! "exact_log2 (INTVAL (operands[2])) >= 0"
"@
{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
#"
--- 2339,2345 ----
(match_operand:SI 2 "const_int_operand" "N,N"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
! "INTVAL (operands[2]) > 0 && exact_log2 (INTVAL (operands[2])) >= 0"
"@
{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
#"
***************
*** 2358,2364 ****
(match_operand:SI 2 "const_int_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
! "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
[(set (match_dup 3)
(div:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
--- 2352,2359 ----
(match_operand:SI 2 "const_int_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
! "INTVAL (operands[2]) > 0 && exact_log2 (INTVAL (operands[2])) >= 0
! && reload_completed"
[(set (match_dup 3)
(div:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
***************
*** 2373,2379 ****
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(div:SI (match_dup 1) (match_dup 2)))]
! "exact_log2 (INTVAL (operands[2])) >= 0"
"@
{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
#"
--- 2368,2374 ----
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(div:SI (match_dup 1) (match_dup 2)))]
! "INTVAL (operands[2]) > 0 && exact_log2 (INTVAL (operands[2])) >= 0"
"@
{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
#"
***************
*** 2387,2393 ****
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(div:SI (match_dup 1) (match_dup 2)))]
! "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
[(set (match_dup 0)
(div:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
--- 2382,2389 ----
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(div:SI (match_dup 1) (match_dup 2)))]
! "INTVAL (operands[2]) > 0 && exact_log2 (INTVAL (operands[2])) >= 0
! && reload_completed"
[(set (match_dup 0)
(div:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
***************
*** 5575,5581 ****
(define_expand "adddi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_arith_cint_operand" "")))]
""
"
{
--- 5571,5577 ----
(define_expand "adddi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
""
"
{
***************
*** 5590,5603 ****
{
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (DImode));
-
- HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
- HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
-
- if (low & 0x8000)
- high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
! emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high)));
emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
DONE;
}
--- 5586,5603 ----
{
rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (DImode));
! HOST_WIDE_INT val = INTVAL (operands[2]);
! HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
! HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
!
! if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
! FAIL;
!
! /* The ordering here is important for the prolog expander.
! When space is allocated from the stack, adding 'low' first may
! produce a temporary deallocation (which would be bad). */
! emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
DONE;
}
***************
*** 5690,5703 ****
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
"
{
! HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
! HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
- if (low & 0x8000)
- high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
-
- operands[3] = GEN_INT (high);
operands[4] = GEN_INT (low);
}")
(define_insn "one_cmpldi2"
--- 5690,5711 ----
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
"
{
! HOST_WIDE_INT val = INTVAL (operands[2]);
! HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
! HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
operands[4] = GEN_INT (low);
+ if (CONST_OK_FOR_LETTER_P (rest, 'L'))
+ operands[3] = GEN_INT (rest);
+ else if (! no_new_pseudos)
+ {
+ operands[3] = gen_reg_rtx (DImode);
+ emit_move_insn (operands[3], operands[2]);
+ emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
+ DONE;
+ }
+ else
+ FAIL;
}")
(define_insn "one_cmpldi2"
***************
*** 5826,5832 ****
(define_expand "subdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
! (match_operand:DI 2 "reg_or_arith_cint_operand" "")))]
""
"
{
--- 5834,5840 ----
(define_expand "subdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
! (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
""
"
{
***************
*** 5985,5990 ****
--- 5993,5999 ----
"
{
if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 0
&& exact_log2 (INTVAL (operands[2])) >= 0)
;
else
***************
*** 5998,6008 ****
"TARGET_POWERPC64"
"
{
! int i = exact_log2 (INTVAL (operands[2]));
rtx temp1;
rtx temp2;
! if (GET_CODE (operands[2]) != CONST_INT || i < 0)
FAIL;
temp1 = gen_reg_rtx (DImode);
--- 6007,6019 ----
"TARGET_POWERPC64"
"
{
! int i;
rtx temp1;
rtx temp2;
! if (GET_CODE (operands[2]) != CONST_INT
! || INTVAL (operands[2]) <= 0
! || (i = exact_log2 (INTVAL (operands[2]))) < 0)
FAIL;
temp1 = gen_reg_rtx (DImode);
***************
*** 6018,6024 ****
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "N")))]
! "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
"sradi %0,%1,%p2\;addze %0,%0"
[(set_attr "length" "8")])
--- 6029,6036 ----
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "const_int_operand" "N")))]
! "TARGET_POWERPC64 && INTVAL (operands[2]) > 0
! && exact_log2 (INTVAL (operands[2])) >= 0"
"sradi %0,%1,%p2\;addze %0,%0"
[(set_attr "length" "8")])
***************
*** 6028,6034 ****
(match_operand:DI 2 "const_int_operand" "N,N"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
! "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
"@
sradi %3,%1,%p2\;addze. %3,%3
#"
--- 6040,6047 ----
(match_operand:DI 2 "const_int_operand" "N,N"))
(const_int 0)))
(clobber (match_scratch:DI 3 "=r,r"))]
! "TARGET_POWERPC64 && INTVAL (operands[2]) > 0
! && exact_log2 (INTVAL (operands[2])) >= 0"
"@
sradi %3,%1,%p2\;addze. %3,%3
#"
***************
*** 6041,6047 ****
(match_operand:DI 2 "const_int_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
! "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
[(set (match_dup 3)
(div:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
--- 6054,6061 ----
(match_operand:DI 2 "const_int_operand" ""))
(const_int 0)))
(clobber (match_scratch:DI 3 ""))]
! "TARGET_POWERPC64 && INTVAL (operands[2]) > 0
! && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
[(set (match_dup 3)
(div:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
***************
*** 6056,6062 ****
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(div:DI (match_dup 1) (match_dup 2)))]
! "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
"@
sradi %0,%1,%p2\;addze. %0,%0
#"
--- 6070,6077 ----
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(div:DI (match_dup 1) (match_dup 2)))]
! "TARGET_POWERPC64 && INTVAL (operands[2]) > 0
! && exact_log2 (INTVAL (operands[2])) >= 0"
"@
sradi %0,%1,%p2\;addze. %0,%0
#"
***************
*** 6070,6076 ****
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(div:DI (match_dup 1) (match_dup 2)))]
! "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
[(set (match_dup 0)
(div:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
--- 6085,6092 ----
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(div:DI (match_dup 1) (match_dup 2)))]
! "TARGET_POWERPC64 && INTVAL (operands[2]) > 0
! && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
[(set (match_dup 0)
(div:DI (match_dup 1) (match_dup 2)))
(set (match_dup 3)