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patch for march/mcpu for mips
- To: gcc-patches at gcc dot gnu dot org
- Subject: patch for march/mcpu for mips
- From: Eric Christopher <echristo at redhat dot com>
- Date: 07 Jul 2001 08:27:04 +0000
I just checked this in as Geoff Keating approved it.
-eric
--
I will not grease the monkey bars
2001-07-05 Eric Christopher <echristo@redhat.com>
* config/mips/mips.h (MASK_MIPS3900): Remove.
(MASK_MIPS16,MASK_NO_CHECK_ZERO_DIV,MASK_CHECK_RANGE_DIV,
MASK_UNINIT_CONST_IN_RODATA): Change for 3900 mask removal.
(TARGET_MIPS3900): Change to use mips_arch.
(TARGET_MIPS4000): New.
(TARGET_MIPS4100): New.
(TARGET_MIPS4300): New.
(TARGET_SWITCHES): Change 3900 and 4650 options to NULL.
(SUBTARGET_TARGET_OPTIONS): Add -march. Change help text
for -mipsX.
(GENERATE_BRANCHLIKELY): Move TARGET_MIPS3900.
(ISA_HAS_BRANCHLIKELY): To here.
(CC1_CPU_SPEC): New.
(CC1_SPEC): Use here. Remove 4650 and 3900 options.
(mips_arch_string): Declare.
(mips_arch): Declare.
(TARGET_OPTIONS): Add -march and -mtune.
* config/mips/mips.c (mips_arch_string): New.
(mips_arch): New.
(override_options): Handle -march for codegen and -mtune
for scheduling. Use mips_arch. Move tx39 target default here.
(mips_parse_cpu): Move error message to override_options.
* config/mips/r3900.h (TARGET_DEFAULT): Remove.
* config/mips/mips.md: Use TARGET_MIPS4000 and TARGET_MIPS4300.
* doc/invoke.texi (Option Summary): Add -march and -mtune entries.
(MIPS Options): Ditto. Change mcpu entry to historical text.
2001-07-05 H.J. Lu (hjl@gnu.org)
* config/mips/mips.c (mips_parse_cpu): New function to parse
-march=*/-mcpu=*.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.121
diff -u -p -w -r1.121 mips.c
--- mips.c 2001/07/04 17:43:17 1.121
+++ mips.c 2001/07/06 07:10:07
@@ -107,6 +107,7 @@ static void abort_with_insn PARAMS ((r
ATTRIBUTE_NORETURN;
static int symbolic_expression_p PARAMS ((rtx));
static void mips_add_gc_roots PARAMS ((void));
+static enum processor_type mips_parse_cpu PARAMS ((const char *));
/* Global variables for machine-dependent things. */
@@ -193,7 +194,13 @@ enum cmp_type branch_type;
static int prev_half_pic_ptrs = 0;
static int prev_half_pic_refs = 0;
-/* which cpu are we scheduling for */
+/* The target cpu for code generation. */
+enum processor_type mips_arch;
+
+/* The target cpu for optimization and scheduling. */
+enum processor_type mips_tune;
+
+/* Historical option for code generation and scheduling. */
enum processor_type mips_cpu;
/* which instruction set architecture to use. */
@@ -207,6 +214,8 @@ int mips_abi;
/* Strings to hold which cpu and instruction set architecture to use. */
const char *mips_cpu_string; /* for -mcpu=<xxx> */
+const char *mips_arch_string; /* for -march=<xxx> */
+const char *mips_tune_string; /* for -mtune=<xxx> */
const char *mips_isa_string; /* for -mips{1,2,3,4} */
const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
@@ -4829,133 +4838,111 @@ override_options ()
greater than that supported by the default processor, then the user gets
an error. Normally, the compiler will just default to the base level cpu
for the indicated isa. */
- if (mips_cpu_string == 0)
- mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
+ if (mips_arch_string == 0)
+ mips_arch_string = MIPS_CPU_STRING_DEFAULT;
+ if (mips_tune_string == 0)
+ mips_tune_string = MIPS_CPU_STRING_DEFAULT;
#endif
/* Identify the processor type. */
- if (mips_cpu_string == 0
- || ! strcmp (mips_cpu_string, "default")
- || ! strcmp (mips_cpu_string, "DEFAULT"))
+
+ if (mips_cpu_string != 0)
+ {
+ mips_cpu = mips_parse_cpu (mips_cpu_string);
+ if (mips_cpu == PROCESSOR_DEFAULT)
+ {
+ error ("bad value (%s) for -mcpu= switch", mips_arch_string);
+ mips_cpu_string = "default";
+ }
+ mips_arch = mips_cpu;
+ mips_tune = mips_cpu;
+ }
+
+ if (mips_arch_string == 0
+ || ! strcmp (mips_arch_string, "default")
+ || ! strcmp (mips_arch_string, "DEFAULT"))
{
switch (mips_isa)
{
default:
- mips_cpu_string = "3000";
- mips_cpu = PROCESSOR_R3000;
+ mips_arch_string = "3000";
+ mips_arch = PROCESSOR_R3000;
break;
case 2:
- mips_cpu_string = "6000";
- mips_cpu = PROCESSOR_R6000;
+ mips_arch_string = "6000";
+ mips_arch = PROCESSOR_R6000;
break;
case 3:
- mips_cpu_string = "4000";
- mips_cpu = PROCESSOR_R4000;
+ mips_arch_string = "4000";
+ mips_arch = PROCESSOR_R4000;
break;
case 4:
- mips_cpu_string = "8000";
- mips_cpu = PROCESSOR_R8000;
+ mips_arch_string = "8000";
+ mips_arch = PROCESSOR_R8000;
break;
}
}
else
{
- const char *p = mips_cpu_string;
- int seen_v = 0;
-
- /* We need to cope with the various "vr" prefixes for the NEC 4300
- and 4100 processors. */
- if (*p == 'v' || *p == 'V')
- seen_v = 1, p++;
-
- if (*p == 'r' || *p == 'R')
- p++;
-
- /* Since there is no difference between a R2000 and R3000 in
- terms of the scheduler, we collapse them into just an R3000. */
-
- mips_cpu = PROCESSOR_DEFAULT;
- switch (*p)
+ mips_arch = mips_parse_cpu (mips_arch_string);
+ if (mips_arch == PROCESSOR_DEFAULT)
{
- case '2':
- if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
- mips_cpu = PROCESSOR_R3000;
- break;
-
- case '3':
- if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
- mips_cpu = PROCESSOR_R3000;
- else if (!strcmp (p, "3900"))
- mips_cpu = PROCESSOR_R3900;
- break;
-
- case '4':
- if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
- mips_cpu = PROCESSOR_R4000;
- /* The vr4100 is a non-FP ISA III processor with some extra
- instructions. */
- else if (!strcmp (p, "4100"))
- {
- mips_cpu = PROCESSOR_R4100;
- target_flags |= MASK_SOFT_FLOAT ;
+ error ("bad value (%s) for -march= switch", mips_arch_string);
+ mips_arch_string = "default";
}
- /* The vr4300 is a standard ISA III processor, but with a different
- pipeline. */
- else if (!strcmp (p, "4300"))
- mips_cpu = PROCESSOR_R4300;
- /* The r4400 is exactly the same as the r4000 from the compiler's
- viewpoint. */
- else if (!strcmp (p, "4400"))
- mips_cpu = PROCESSOR_R4000;
- else if (!strcmp (p, "4600"))
- mips_cpu = PROCESSOR_R4600;
- else if (!strcmp (p, "4650"))
- mips_cpu = PROCESSOR_R4650;
- break;
-
- case '5':
- if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
- mips_cpu = PROCESSOR_R5000;
+ }
+ if (mips_tune_string == 0
+ || ! strcmp (mips_tune_string, "default")
+ || ! strcmp (mips_tune_string, "DEFAULT"))
+ {
+ if (mips_arch != PROCESSOR_DEFAULT)
+ mips_tune == mips_arch;
+ else
+ switch (mips_isa)
+ {
+ default:
+ mips_tune_string = "3000";
+ mips_tune = PROCESSOR_R3000;
break;
-
- case '6':
- if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
- mips_cpu = PROCESSOR_R6000;
+ case 2:
+ mips_tune_string = "6000";
+ mips_tune = PROCESSOR_R6000;
break;
-
- case '8':
- if (!strcmp (p, "8000"))
- mips_cpu = PROCESSOR_R8000;
+ case 3:
+ mips_tune_string = "4000";
+ mips_tune = PROCESSOR_R4000;
break;
-
- case 'o':
- if (!strcmp (p, "orion"))
- mips_cpu = PROCESSOR_R4600;
+ case 4:
+ mips_tune_string = "8000";
+ mips_tune = PROCESSOR_R8000;
break;
}
- if (seen_v
- && mips_cpu != PROCESSOR_R4300
- && mips_cpu != PROCESSOR_R4100
- && mips_cpu != PROCESSOR_R5000)
- mips_cpu = PROCESSOR_DEFAULT;
-
- if (mips_cpu == PROCESSOR_DEFAULT)
+ }
+ else
{
- error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
- mips_cpu_string = "default";
+ mips_tune = mips_parse_cpu (mips_tune_string);
+ if (mips_tune == PROCESSOR_DEFAULT)
+ {
+ error ("bad value (%s) for -mtune= switch", mips_tune_string);
+ mips_tune_string = "default";
}
}
+
+ /* Handle processor configuration based on architecture. */
+ if (TARGET_MIPS4100 || TARGET_MIPS3900)
+ target_flags |= MASK_SOFT_FLOAT;
+
- if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
- || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
- || ((mips_cpu == PROCESSOR_R4000
- || mips_cpu == PROCESSOR_R4100
- || mips_cpu == PROCESSOR_R4300
- || mips_cpu == PROCESSOR_R4600
- || mips_cpu == PROCESSOR_R4650)
+ if ((mips_arch == PROCESSOR_R3000 && (mips_isa != 1))
+ || (mips_arch == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
+ || ((mips_arch == PROCESSOR_R4000
+ || mips_arch == PROCESSOR_R4100
+ || mips_arch == PROCESSOR_R4300
+ || mips_arch == PROCESSOR_R4600
+ || mips_arch == PROCESSOR_R4650)
&& mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
- error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
+ error ("-march=%s does not support -mips%d", mips_arch_string, mips_isa);
/* make sure sizes of ints/longs/etc. are ok */
if (! ISA_HAS_64BIT_REGS)
@@ -6068,9 +6055,9 @@ mips_asm_file_start (stream)
asm_out_data_file = asm_out_text_file = stream;
if (flag_verbose_asm)
- fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
+ fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
ASM_COMMENT_START,
- mips_section_threshold, mips_cpu_string, mips_isa);
+ mips_section_threshold, mips_arch_string, mips_isa);
}
/* If we are optimizing the global pointer, emit the text section now and any
@@ -9729,4 +9716,89 @@ mips_add_gc_roots ()
ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
+}
+
+static enum processor_type
+mips_parse_cpu (cpu_string)
+ const char *cpu_string;
+{
+ const char *p = cpu_string;
+ int seen_v = 0;
+ enum processor_type cpu;
+
+ /* We need to cope with the various "vr" prefixes for the NEC 4300
+ and 4100 processors. */
+ if (*p == 'v' || *p == 'V')
+ seen_v = 1, p++;
+
+ if (*p == 'r' || *p == 'R')
+ p++;
+
+ /* Since there is no difference between a R2000 and R3000 in
+ terms of the scheduler, we collapse them into just an R3000. */
+
+ cpu = PROCESSOR_DEFAULT;
+ switch (*p)
+ {
+ case '2':
+ if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
+ cpu = PROCESSOR_R3000;
+ break;
+
+ case '3':
+ if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
+ cpu = PROCESSOR_R3000;
+ else if (!strcmp (p, "3900"))
+ cpu = PROCESSOR_R3900;
+ break;
+
+ case '4':
+ if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
+ cpu = PROCESSOR_R4000;
+ /* The vr4100 is a non-FP ISA III processor with some extra
+ instructions. */
+ else if (!strcmp (p, "4100"))
+ cpu = PROCESSOR_R4100;
+ /* The vr4300 is a standard ISA III processor, but with a different
+ pipeline. */
+ else if (!strcmp (p, "4300"))
+ cpu = PROCESSOR_R4300;
+ /* The r4400 is exactly the same as the r4000 from the compiler's
+ viewpoint. */
+ else if (!strcmp (p, "4400"))
+ cpu = PROCESSOR_R4000;
+ else if (!strcmp (p, "4600"))
+ cpu = PROCESSOR_R4600;
+ else if (!strcmp (p, "4650"))
+ cpu = PROCESSOR_R4650;
+ break;
+
+ case '5':
+ if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
+ cpu = PROCESSOR_R5000;
+ break;
+
+ case '6':
+ if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
+ cpu = PROCESSOR_R6000;
+ break;
+
+ case '8':
+ if (!strcmp (p, "8000"))
+ cpu = PROCESSOR_R8000;
+ break;
+
+ case 'o':
+ if (!strcmp (p, "orion"))
+ cpu = PROCESSOR_R4600;
+ break;
+ }
+
+ if (seen_v
+ && cpu != PROCESSOR_R4300
+ && cpu != PROCESSOR_R4100
+ && cpu != PROCESSOR_R5000)
+ cpu = PROCESSOR_DEFAULT;
+
+ return cpu;
}
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.114
diff -u -p -w -r1.114 mips.h
--- mips.h 2001/06/26 06:36:37 1.114
+++ mips.h 2001/07/06 07:10:14
@@ -133,13 +133,17 @@ extern int mips_branch_likely; /* emit
extern int mips_dbx_regno[]; /* Map register # to debug register # */
extern struct rtx_def *branch_cmp[2]; /* operands for compare */
extern enum cmp_type branch_type; /* what type of branch to use */
-extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
+extern enum processor_type mips_arch; /* which cpu to codegen for */
+extern enum processor_type mips_tune; /* which cpu to schedule for */
+extern enum processor_type mips_cpu; /* historical codegen/sched */
extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
extern int mips_isa; /* architectural level */
extern int mips16; /* whether generating mips16 code */
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
+extern const char *mips_arch_string; /* for -march=<xxx> */
+extern const char *mips_tune_string; /* for -mtune=<xxx> */
extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */
@@ -212,14 +216,13 @@ extern void sbss_section PARAMS ((void)
#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
-#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
-#define MASK_MIPS16 0x00200000 /* Generate mips16 code */
+#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
#define MASK_NO_CHECK_ZERO_DIV \
- 0x00400000 /* divide by zero checking */
+ 0x00200000 /* divide by zero checking */
#define MASK_CHECK_RANGE_DIV \
- 0x00800000 /* divide result range checking */
+ 0x00400000 /* divide result range checking */
#define MASK_UNINIT_CONST_IN_RODATA \
- 0x01000000 /* Store uninitialized
+ 0x00800000 /* Store uninitialized
consts in rodata */
/* Debug switches, not documented */
@@ -246,9 +249,6 @@ extern void sbss_section PARAMS ((void)
/* Mips vs. GNU linker */
#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
-/* generate mips 3900 insns */
-#define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
-
/* Mips vs. GNU assembler */
#define TARGET_GAS (target_flags & MASK_GAS)
#define TARGET_MIPS_AS (!TARGET_GAS)
@@ -330,6 +330,19 @@ extern void sbss_section PARAMS ((void)
/* Generate mips16 code */
#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
+/* Architecture target defines. */
+#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
+#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
+#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
+#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
+
+/* Scheduling target defines. */
+#define TUNE_MIPS3000 (mips_cpu == PROCESSOR_R3000)
+#define TUNE_MIPS3900 (mips_cpu == PROCESSOR_R3900)
+#define TUNE_MIPS4000 (mips_cpu == PROCESSOR_R4000)
+#define TUNE_MIPS5000 (mips_cpu == PROCESSOR_R5000)
+#define TUNE_MIPS6000 (mips_cpu == PROCESSOR_R6000)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
@@ -430,10 +443,10 @@ extern void sbss_section PARAMS ((void)
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
- {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
- N_("Optimize for 4650")}, \
- {"3900", MASK_MIPS3900, \
+ {"3900", 0, \
N_("Optimize for 3900")}, \
+ {"4650", 0, \
+ N_("Optimize for 4650")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
@@ -567,8 +580,12 @@ extern void sbss_section PARAMS ((void)
SUBTARGET_TARGET_OPTIONS \
{ "cpu=", &mips_cpu_string, \
N_("Specify CPU for scheduling purposes")}, \
+ { "tune=", &mips_tune_string, \
+ N_("Specify CPU for scheduling purposes")}, \
+ { "arch=", &mips_arch_string, \
+ N_("Specify CPU for code generation purposes")}, \
{ "ips", &mips_isa_string, \
- N_("Specify MIPS ISA")}, \
+ N_("Specify a Standard MIPS ISA")}, \
{ "entry", &mips_entry_string, \
N_("Use mips16 entry/exit psuedo ops")}, \
{ "no-mips16", &mips_no_mips16_string, \
@@ -580,7 +597,7 @@ extern void sbss_section PARAMS ((void)
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
-#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
+#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
/* Generate three-operand multiply instructions for both SImode and DImode. */
#define GENERATE_MULT3 (TARGET_MIPS3900 \
@@ -597,7 +614,10 @@ extern void sbss_section PARAMS ((void)
)
/* ISA has branch likely instructions (eg. mips2). */
-#define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
+/* Disable branchlikely for tx39 until compare rewrite. They haven't
+ been generated up to this point. */
+#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
+ /* || TARGET_MIPS3900 */)
/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE (mips_isa == 4 \
@@ -791,7 +811,7 @@ while (0)
/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
assembler. */
-#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
+#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
GAS_ASM_SPEC as the default, depending upon the value of
@@ -909,6 +929,16 @@ while (0)
#define SUBTARGET_CC1_SPEC ""
#endif
+/* Deal with historic options. */
+#ifndef CC1_CPU_SPEC
+#define CC1_CPU_SPEC "\
+%{!mcpu*: \
+%{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
+%n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
+%{m4650:-march=r4650 -mmad -msingle-float \
+%n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
+#endif
+
/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
#ifndef CC1_SPEC
@@ -920,15 +950,14 @@ while (0)
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
%{mint64|mlong64|mlong32:-mexplicit-type-size }\
-%{m4650:-mcpu=r4650} \
-%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{pic-none: -mno-half-pic} \
%{pic-lib: -mhalf-pic} \
%{pic-extern: -mhalf-pic} \
%{pic-calls: -mhalf-pic} \
%{save-temps: } \
-%(subtarget_cc1_spec) "
+%(subtarget_cc1_spec) \
+%(cc1_cpu_spec)"
#endif
/* Preprocessor specs. */
@@ -3455,10 +3484,10 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode || xmode == DFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (TUNE_MIPS3000 \
+ || TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (3); \
else \
return COSTS_N_INSNS (6); \
@@ -3481,11 +3510,11 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900 \
- || mips_cpu == PROCESSOR_R5000) \
+ if (TUNE_MIPS3000 \
+ || TUNE_MIPS3900 \
+ || TUNE_MIPS5000) \
return COSTS_N_INSNS (4); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (7); \
@@ -3493,23 +3522,23 @@ while (0)
\
if (xmode == DFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900 \
- || mips_cpu == PROCESSOR_R5000) \
+ if (TUNE_MIPS3000 \
+ || TUNE_MIPS3900 \
+ || TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (6); \
else \
return COSTS_N_INSNS (8); \
} \
\
- if (mips_cpu == PROCESSOR_R3000) \
+ if (TUNE_MIPS3000) \
return COSTS_N_INSNS (12); \
- else if (mips_cpu == PROCESSOR_R3900) \
+ else if (TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (17); \
- else if (mips_cpu == PROCESSOR_R5000) \
+ else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (10); \
@@ -3521,10 +3550,10 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (TUNE_MIPS3000 \
+ || TUNE_MIPS3900) \
return COSTS_N_INSNS (12); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (15); \
else \
return COSTS_N_INSNS (23); \
@@ -3532,10 +3561,10 @@ while (0)
\
if (xmode == DFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (TUNE_MIPS3000 \
+ || TUNE_MIPS3900) \
return COSTS_N_INSNS (19); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (16); \
else \
return COSTS_N_INSNS (36); \
@@ -3545,12 +3574,12 @@ while (0)
\
case UDIV: \
case UMOD: \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (TUNE_MIPS3000 \
+ || TUNE_MIPS3900) \
return COSTS_N_INSNS (35); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (38); \
- else if (mips_cpu == PROCESSOR_R5000) \
+ else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (36); \
else \
return COSTS_N_INSNS (69); \
@@ -3668,7 +3697,7 @@ while (0)
/* ??? Fix this to be right for the R8000. */
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
- (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
+ (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
+ memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
/* Define if copies to/from condition code registers should be avoided.
@@ -3684,7 +3713,7 @@ while (0)
/* ??? Fix this to be right for the R8000. */
#define BRANCH_COST \
((! TARGET_MIPS16 \
- && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
+ && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
? 2 : 1)
/* A C statement (sans semicolon) to update the integer variable COST
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.98
diff -u -p -w -r1.98 mips.md
--- mips.md 2001/07/04 17:43:17 1.98
+++ mips.md 2001/07/06 07:10:20
@@ -1626,7 +1626,7 @@
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (mips_cpu != PROCESSOR_R4300)
+ if (TARGET_MIPS4300)
emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
@@ -1637,7 +1637,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
"mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")])
@@ -1646,7 +1646,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
"*
{
output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
@@ -1665,7 +1665,7 @@
"TARGET_HARD_FLOAT"
"
{
- if (mips_cpu != PROCESSOR_R4300)
+ if (!TARGET_MIPS4300)
emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
@@ -1676,7 +1676,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
"mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
@@ -1685,7 +1685,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && TARGET_MIPS4300"
"*
{
output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
@@ -1713,7 +1713,7 @@
{
if (HAVE_mulsi3_mult3)
emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
- else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
+ else if (!TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
@@ -1746,7 +1746,7 @@
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=a"))]
- "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
+ "!TARGET_MIPS4000 || TARGET_MIPS16"
"mult\\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -1758,7 +1758,7 @@
(clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=l"))
(clobber (match_scratch:SI 5 "=a"))]
- "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16"
+ "TARGET_MIPS4000 && !TARGET_MIPS16"
"*
{
rtx xoperands[10];
@@ -1855,7 +1855,7 @@
"
{
- if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)
+ if (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)
emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
@@ -1873,7 +1873,7 @@
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16"
+ "TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
"dmult\\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -1885,7 +1885,7 @@
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l"))
(clobber (match_scratch:DI 5 "=a"))]
- "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)"
+ "TARGET_64BIT && (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)"
"*
{
if (GENERATE_MULT3)
Index: config/mips/r3900.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/r3900.h,v
retrieving revision 1.8
diff -u -p -w -r1.8 r3900.h
--- r3900.h 2000/02/26 21:35:46 1.8
+++ r3900.h 2001/07/06 07:10:20
@@ -43,7 +43,6 @@ Boston, MA 02111-1307, USA. */
%{msingle-float:%{msoft-float: \
%e-msingle-float and -msoft-float can not both be specified.}}"
-#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_MIPS3900)
#define MIPS_CPU_STRING_DEFAULT "R3900"
#define MIPS_ISA_DEFAULT 1
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.33
diff -u -p -w -r1.33 invoke.texi
--- invoke.texi 2001/07/05 19:38:30 1.33
+++ invoke.texi 2001/07/06 07:10:34
@@ -447,8 +447,8 @@ in the following sections.
@emph{MIPS Options}
@gccoptlist{
--mabicalls -mcpu=@var{cpu-type} @gol
--membedded-data -muninit-const-in-rodata @gol
+-mabicalls -march=@var{cpu-type} -mtune=@var{cpu=type} @gol
+-mcpu=@var{cpu-type} -membedded-data -muninit-const-in-rodata @gol
-membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol
-mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol
@@ -935,10 +935,17 @@ names @samp{c9x} and @samp{iso9899:199x}
Default, ISO C89 plus GNU extensions (including some C99 features).
@item gnu99
-@itemx gnu9x
-ISO C99 plus GNU extensions. When ISO C99 is fully implemented in GCC,
-this will become the default. The name @samp{gnu9x} is deprecated.
+iso9899:1999 + gnu extensions
+@item iso9899:199x
+same as @option{-std=iso9899:1999}, deprecated
+
+@item c9x
+same as @option{-std=iso9899:1999}, deprecated
+
+@item gnu9x
+same as @option{-std=gnu99}, deprecated
+
@end table
Even when this option is not specified, you can still use some of the
@@ -7031,8 +7038,19 @@ option @option{-mhc-struct-return}.
These @samp{-m} options are defined for the MIPS family of computers:
@table @gcctabopt
-@item -mcpu=@var{cpu-type}
-@opindex mcpu
+
+@item -march=@var{cpu-type}
+@opindex march
+Assume the defaults for the machine type @var{cpu-type} when generating
+instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
+@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
+@samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000}, @samp{r8000},
+and @samp{orion}. Additionally, the @samp{r2000}, @samp{r3000},
+@samp{r4000}, @samp{r5000}, and @samp{r6000} can be abbreviated as
+@samp{r2k} (or @samp{r2K}), @samp{r3k}, etc.
+
+@item -mtune=@var{cpu-type}
+@opindex mtune
Assume the defaults for the machine type @var{cpu-type} when scheduling
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
@@ -7044,6 +7062,10 @@ and @samp{orion}. Additionally, the @sa
chip, the compiler will not generate any code that does not meet level 1
of the MIPS ISA (instruction set architecture) without a @option{-mipsX}
or @option{-mabi} switch being used.
+
+@item -mcpu=@var{cpu-type}
+@opindex mcpu
+This is identical to specifying both @option{-march} and @option{-mtune}.
@item -mips1
@opindex mips1