This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
2.95: Fix -mcpu=ultrasparc problem
- To: <gcc-patches at gcc dot gnu dot org>
- Subject: 2.95: Fix -mcpu=ultrasparc problem
- From: Bernd Schmidt <bernds at redhat dot com>
- Date: Tue, 22 May 2001 16:53:45 +0100 (BST)
This bug seems to get reported a lot. When -mcpu=ultrasparc is used with
a 2.95.x sparc compiler, the generated code can occasionally contain
unaligned DFmode loads, which are invalid.
The relevant code has changed a lot since then. This patch is an attempt
to extract the bugfix from a larger set of changes made by Jakub Jelinek.
I haven't tested this very much other than with the gcc testsuite (it
seems to help a lot with -mcpu=ultrasparc); I'd appreciate if someone who
uses sparc as their main platform could compile a few interesting packages
with an up-to-date 2.95 branch compiler to see whether it still works
(yes, I'm slightly nervous about this patch).
Bernd
* sparc.md (movsf, movdf): Allow constant to integer reg moves.
(movsf, movdf splitters): Always split if there's an alignment
problem.
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.71.4.5
diff -u -p -r1.71.4.5 sparc.md
--- config/sparc/sparc.md 2001/03/30 14:06:36 1.71.4.5
+++ config/sparc/sparc.md 2001/05/22 15:31:53
@@ -2899,6 +2899,11 @@
crashes in output_constant_pool. */
if (operands [1] == const0_rtx)
operands[1] = CONST0_RTX (SFmode);
+ /* We are able to build any SF constant in integer registers
+ with at most 2 instructions. */
+ if (REGNO (operands[0]) < 32)
+ goto movsf_is_ok;
+
operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
operands[1]));
}
@@ -3093,6 +3098,9 @@
crashes in output_constant_pool. */
if (operands [1] == const0_rtx)
operands[1] = CONST0_RTX (DFmode);
+ if (REGNO (operands[0]) < 32)
+ goto movdf_is_ok;
+
operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
operands[1]));
}
@@ -3277,17 +3285,11 @@
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))]
- "((! TARGET_V9
- || (! TARGET_ARCH64
- && ((GET_CODE (operands[0]) == REG
- && REGNO (operands[0]) < 32)
- || (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
- && REGNO (SUBREG_REG (operands[0])) < 32))))
- && (reload_completed
- && (((REGNO (operands[0])) % 2) != 0
- || ! mem_min_alignment (operands[1], 8))
- && offsettable_memref_p (operands[1])))"
+ "reload_completed
+ && ! TARGET_ARCH64
+ && (((REGNO (operands[0]) % 2) != 0)
+ || ! mem_min_alignment (operands[1], 8))
+ && offsettable_memref_p (operands[1])"
[(clobber (const_int 0))]
"
{
@@ -3318,17 +3320,11 @@
(define_split
[(set (match_operand:DF 0 "memory_operand" "")
(match_operand:DF 1 "register_operand" ""))]
- "((! TARGET_V9
- || (! TARGET_ARCH64
- && ((GET_CODE (operands[1]) == REG
- && REGNO (operands[1]) < 32)
- || (GET_CODE (operands[1]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[1])) == REG
- && REGNO (SUBREG_REG (operands[1])) < 32))))
- && (reload_completed
- && (((REGNO (operands[1])) % 2) != 0
- || ! mem_min_alignment (operands[0], 8))
- && offsettable_memref_p (operands[0])))"
+ "reload_completed
+ && ! TARGET_ARCH64
+ && (((REGNO (operands[1]) % 2) != 0)
+ || ! mem_min_alignment (operands[0], 8))
+ && offsettable_memref_p (operands[0])"
[(clobber (const_int 0))]
"
{