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[PATCH]: Generate bit/bita/bitb instructions for HC11/HC12
- To: gcc-patches at gcc dot gnu dot org
- Subject: [PATCH]: Generate bit/bita/bitb instructions for HC11/HC12
- From: Stephane Carrez <Stephane dot Carrez at worldnet dot fr>
- Date: Thu, 03 May 2001 23:18:37 +0200
Hi!
The following patch adds new patterns for HC11/HC12 to generate bit-test
instructions.
I've committed the patch on mainline and 3_0-branch.
Stephane
2001-05-03 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/m68hc11/m68hc11.md ("bitcmpqi"): New pattern for bitb
instruction.
("bitcmpqi2"): New pattern for bit-extract and test.
("bitcmphi"): New pattern for bitb/bita instructions.
Index: config/m68hc11/m68hc11.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68hc11/m68hc11.md,v
retrieving revision 1.4
diff -u -p -r1.4 m68hc11.md
--- m68hc11.md 2001/05/03 19:56:46 1.4
+++ m68hc11.md 2001/05/03 20:38:01
@@ -383,6 +383,87 @@
DONE;
}")
+(define_insn "bitcmpqi"
+ [(set (cc0)
+ (and:QI (match_operand:QI 0 "tst_operand" "d,d,d")
+ (match_operand:QI 1 "cmp_operand" "im,*A,u")))]
+ ""
+ "@
+ bitb\\t%1
+ #
+ bitb\\t%1")
+
+(define_insn "bitcmpqi_z_used"
+ [(set (cc0)
+ (and:QI (match_operand:QI 0 "tst_operand" "d")
+ (match_operand:QI 1 "cmp_operand" "m")))
+ (use (match_operand:HI 2 "hard_reg_operand" "xy"))
+ (use (reg:HI 11))]
+ ""
+ "#")
+
+(define_split /* "bitcmpqi_z_used" */
+ [(set (cc0)
+ (and:QI (match_operand:QI 0 "tst_operand" "d")
+ (match_operand:QI 1 "cmp_operand" "m")))
+ (use (match_operand:HI 2 "hard_reg_operand" "xy"))
+ (use (reg:HI 11))]
+ "z_replacement_completed == 2"
+ [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2))
+ (set (match_dup 2) (match_dup 3))
+ (set (cc0) (and:QI (match_dup 0) (match_dup 1)))
+ (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI 3))))]
+ "operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);")
+
+(define_insn "bitcmphi"
+ [(set (cc0)
+ (and:HI (match_operand:HI 0 "tst_operand" "d")
+ (match_operand:HI 1 "const_int_operand" "i")))]
+ "(INTVAL (operands[1]) & 0x0ff) == 0
+ || (INTVAL (operands[1]) & 0x0ff00) == 0"
+ "*
+{
+ if ((INTVAL (operands[1]) & 0x0ff) == 0)
+ return \"bita\\t%h1\";
+ else
+ return \"bitb\\t%1\";
+}")
+
+(define_insn "bitcmpqi_12"
+ [(set (cc0)
+ (zero_extract (match_operand:HI 0 "tst_operand" "d")
+ (match_operand:HI 1 "const_int_operand" "i")
+ (match_operand:HI 2 "const_int_operand" "i")))]
+ "(unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 8
+ || (((unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 16)
+ && (unsigned) INTVAL (operands[2]) >= 8)"
+ "*
+{
+ rtx ops[1];
+ int mask;
+ int startpos = INTVAL (operands[2]);
+ int bitsize = INTVAL (operands[1]);
+
+ if (startpos >= 8)
+ {
+ startpos -= 8;
+ mask = (1 << (startpos + bitsize)) - 1;
+ mask &= ~((1 << startpos) - 1);
+
+ ops[0] = GEN_INT (mask);
+ output_asm_insn (\"bita\\t%0\", ops);
+ }
+ else
+ {
+ mask = (1 << (startpos + bitsize)) - 1;
+ mask &= ~((1 << startpos) - 1);
+
+ ops[0] = GEN_INT (mask);
+ output_asm_insn (\"bitb\\t%0\", ops);
+ }
+ return \"\";
+}")
+
(define_insn "cmpqi_1"
[(set (cc0)
(compare (match_operand:QI 0 "tst_operand" "d,d,*x*y,*x*y")