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SSE fixes commited


Hi
I've did some testing of the SSE support after the merger and found some
problems (I forgot to merge some hunks and had some ordering problem on the
validating of patches for commit).  All of them are trivial, so I am going to
commit this as obvious bugfix.

First part of patch avoids fp conditional move expander to create unneeded
pseudos and thus crash when it is called from sse conditional move splitter
post-reload.
Second part contains few assorted fixes - I forgot update PREDICATE_CODES,
the float?i?f splitter is somewhat overactive etc.

With this patch, I can bootstrap/pass make check with -msse2. There are no
new regressions and some disappears.

Honza

Sat Mar  3 19:33:45 CET 2001  Jan Hubicka  <jh@suse.cz>
	* i386.c (ix86_expand_fp_compare): Delay creating of scratch register
	until when it is really needed.
	(ix86_expand_compare): Update call of ix86_expand_fp_compare.
	* i386.h (PREDICATE_CODES): Add all codes for sse_comparison_operator
	* i386.md (float?i?f splitter): Don't force source operand to memory
	for SSE.
	(sse_movdfcc): Fix constraint.
	(sse_movdfcc splitter): Handle properly the second alternative.

Index: i386/i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.228
diff -c -3 -p -r1.228 i386.c
*************** ix86_expand_fp_compare (code, op0, op1, 
*** 5196,5201 ****
--- 5246,5253 ----
  	{
  	  tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
  	  tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9);
+ 	  if (!scratch)
+ 	    scratch = gen_reg_rtx (HImode);
  	  emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
  	  emit_insn (gen_x86_sahf_1 (scratch));
  	}
*************** ix86_expand_fp_compare (code, op0, op1, 
*** 5217,5222 ****
--- 5269,5276 ----
        /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first.  */
        tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
        tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9);
+       if (!scratch)
+ 	scratch = gen_reg_rtx (HImode);
        emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
  
        /* In the unordered case, we have to check C2 for NaN's, which
*************** ix86_expand_compare (code, second_test, 
*** 5357,5363 ****
      *bypass_test = NULL_RTX;
  
    if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
!     ret = ix86_expand_fp_compare (code, op0, op1, gen_reg_rtx (HImode),
  				  second_test, bypass_test);
    else
      ret = ix86_expand_int_compare (code, op0, op1);
--- 5411,5417 ----
      *bypass_test = NULL_RTX;
  
    if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
!     ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
  				  second_test, bypass_test);
    else
      ret = ix86_expand_int_compare (code, op0, op1);
Index: i386/i386.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.h,v
retrieving revision 1.159
diff -c -3 -p -r1.159 i386.h
*** i386.h	2001/02/28 18:34:35	1.159
--- i386.h	2001/03/03 18:23:05
*************** do { long l;						\
*** 2869,2875 ****
    {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
  				 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE,	\
  				 GE, UNGE, LTGT, UNEQ}},		\
!   {"sse_comparison_operator", {EQ, LT, LE, UNORDERED }},		\
    {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU,	\
  			       GTU, UNORDERED, ORDERED, UNLE, UNLT,	\
  			       UNGE, UNGT, LTGT, UNEQ }},		\
--- 2874,2882 ----
    {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
  				 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE,	\
  				 GE, UNGE, LTGT, UNEQ}},		\
!   {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT,	\
! 			       ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT	\
! 			       }},					\
    {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU,	\
  			       GTU, UNORDERED, ORDERED, UNLE, UNLT,	\
  			       UNGE, UNGT, LTGT, UNEQ }},		\
Index: i386/i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.227
diff -c -3 -p -r1.227 i386.md
*** i386.md	2001/02/28 18:34:35	1.227
--- i386.md	2001/03/03 18:23:08
***************
*** 4450,4456 ****
  (define_split
    [(set (match_operand 0 "register_operand" "")
  	(float (match_operand 1 "register_operand" "")))]
!   "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
    [(const_int 0)]
    "
  {
--- 4235,4242 ----
  (define_split
    [(set (match_operand 0 "register_operand" "")
  	(float (match_operand 1 "register_operand" "")))]
!   "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
!    && FP_REG_P (operands[0])"
    [(const_int 0)]
    "
  {
***************
*** 12506,12512 ****
  			 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
  		      (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
  		      (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
!    (clobber (match_scratch:DF 6 "=2,&5,X,X,X,X,X,X,X,X"))
     (clobber (reg:CC 17))]
    "TARGET_SSE2
     && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
--- 12374,12380 ----
  			 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
  		      (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
  		      (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
!    (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
     (clobber (reg:CC 17))]
    "TARGET_SSE2
     && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
***************
*** 12547,12553 ****
  			 (match_operand 5 "nonimmediate_operand" "")])
  		      (match_operand 2 "register_operand" "")
  		      (match_operand 3 "register_operand" "")))
!    (clobber (match_dup 2))
     (clobber (reg:CC 17))]
    "SSE_REG_P (operands[0]) && reload_completed"
    [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
--- 12415,12421 ----
  			 (match_operand 5 "nonimmediate_operand" "")])
  		      (match_operand 2 "register_operand" "")
  		      (match_operand 3 "register_operand" "")))
!    (clobber (match_operand 6 "" ""))
     (clobber (reg:CC 17))]
    "SSE_REG_P (operands[0]) && reload_completed"
    [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))


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