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SSE sqrt patterns
- To: Richard Henderson <rth at redhat dot com>, gcc-patches at gcc dot gnu dot org, patches at x86-64 dot org
- Subject: SSE sqrt patterns
- From: Jan Hubicka <jh at suse dot cz>
- Date: Tue, 13 Feb 2001 18:53:16 +0100
Hi
The sqrt support is trivial, since SSE do have instruction in question.
The neg/abs will probably need to wait till next week.
Tue Feb 13 18:50:49 CET 2001 Jan Hubicka <jh@suse.cz>
* i386.c (sqrt?f2): Change to expander.
(sqrt?f2_1, sqrt?f2_sse_only, sqrt?f2_i387): New.
Index: i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.216
diff -c -3 -p -r1.216 i386.c
*** i386.c 2001/02/13 13:54:44 1.216
--- i386.c 2001/02/13 17:45:39
***************
*** 10760,10779 ****
;; FPU special functions.
! (define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "direct")])
! (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (TARGET_IEEE_FP || flag_fast_math) "
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
--- 10857,10939 ----
;; FPU special functions.
! (define_expand "sqrtsf2"
! [(set (match_operand:SF 0 "register_operand" "")
! (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
! "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
! "
! {
! if (!TARGET_SSE)
! operands[1] = force_reg (SFmode, operands[1]);
! }")
!
! (define_insn "sqrtsf2_1"
! [(set (match_operand:SF 0 "register_operand" "=f#Y,Y#f")
! (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (TARGET_SSE && TARGET_MIX_SSE_I387)"
! "@
! fsqrt
! sqrtss\\t{%1, %0|%0, %1}"
! [(set_attr "type" "fpspc,sse")
! (set_attr "mode" "SF,SF")
! (set_attr "athlon_decode" "direct,*")])
!
! (define_insn "sqrtsf2_1_sse_only"
! [(set (match_operand:SF 0 "register_operand" "=Y")
! (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "Ym")))]
! "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
! "sqrtss\\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")
! (set_attr "athlon_decode" "*")])
!
! (define_insn "sqrtsf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "direct")])
! (define_expand "sqrtdf2"
! [(set (match_operand:DF 0 "register_operand" "")
! (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
! "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
! "
! {
! if (!TARGET_SSE)
! operands[1] = force_reg (SFmode, operands[1]);
! }")
!
! (define_insn "sqrtdf2_1"
! [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
! (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (TARGET_SSE && TARGET_MIX_SSE_I387)"
! "@
! fsqrt
! sqrtsd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "fpspc,sse")
! (set_attr "mode" "DF,DF")
! (set_attr "athlon_decode" "direct,*")])
!
! (define_insn "sqrtdf2_1_sse_only"
! [(set (match_operand:DF 0 "register_operand" "=Y")
! (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
! "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
! "sqrtsd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "DF")
! (set_attr "athlon_decode" "*")])
!
! (define_insn "sqrtdf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")