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Re: Splitting call_insns
On Nov 25, 2000, Alexandre Oliva <aoliva@redhat.com> wrote:
> On Nov 24, 2000, Richard Henderson <rth@redhat.com> wrote:
>> I think you'd be better off running split_all_insns at the
>> beginning of machine_dependent_reorg than have two methods
>> of call generation.
> But I'll look into splitting insns at machine_dependent_reorg()
> entry. Probably only if optimize == 0.
Here's the patch. While I was at it, I also fixed sibcalls so that
they may, for whatever reason, use registers other than r0 for the
call address. I'm still testing this but, assuming there are no
regressions, ok to install?
Index: gcc/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (reg_class_from_letter): Assign `k' to SIBCALL_REGS.
(machine_dependent_reorg): Split all insns.
* config/sh/sh.h (CONDITIONAL_REGISTER_USAGE): Compute
reg_class_contents[SIBCALL_REGS].
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add SIBCALL_REGS.
* config/sh/sh.md (calli_pcrel, call_pcrel, call_valuei_pcrel,
call_value_pcrel, call, call_value, sibcall): Match even when
not optimizing.
(sibcalli_pcrel, sibcall_pcrel): Likewise. Use constraint `k'
for call address.
(sibcalli): Likewise.
Index: gcc/config/sh/sh.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.c,v
retrieving revision 1.78
diff -u -p -r1.78 sh.c
--- gcc/config/sh/sh.c 2000/11/25 04:42:27 1.78
+++ gcc/config/sh/sh.c 2000/11/25 07:10:07
@@ -120,7 +120,7 @@ enum reg_class reg_class_from_letter[] =
{
/* a */ ALL_REGS, /* b */ NO_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
/* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
- /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
+ /* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
/* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
/* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
/* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
@@ -2909,6 +2909,9 @@ machine_dependent_reorg (first)
int num_mova;
rtx r0_rtx = gen_rtx_REG (Pmode, 0);
rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
+
+ if (! optimize)
+ split_all_insns (0);
/* If relaxing, generate pseudo-ops to associate function calls with
the symbols they call. It does no harm to not generate these
Index: gcc/config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.h,v
retrieving revision 1.88
diff -u -p -r1.88 sh.h
--- gcc/config/sh/sh.h 2000/11/25 06:35:09 1.88
+++ gcc/config/sh/sh.h 2000/11/25 07:10:08
@@ -63,17 +63,17 @@ extern int code_for_indirect_jump_scratc
/* We can not debug without a frame pointer. */
/* #define CAN_DEBUG_WITHOUT_FP */
-#define CONDITIONAL_REGISTER_USAGE \
+#define CONDITIONAL_REGISTER_USAGE do \
+{ \
+ int regno; \
if (! TARGET_SH4 || ! TARGET_FMOVD) \
{ \
- int regno; \
for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
if (! TARGET_SH4) \
{ \
if (! TARGET_SH3E) \
{ \
- int regno; \
for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
@@ -87,7 +87,11 @@ extern int code_for_indirect_jump_scratc
{ \
call_used_regs[MACH_REG] = 0; \
call_used_regs[MACL_REG] = 0; \
- }
+ } \
+ for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
+ if (! fixed_regs[regno] && call_used_regs [regno]) \
+ SET_HARD_REG_BIT (reg_class_contents [SIBCALL_REGS], regno); \
+} while (0)
/* ??? Need to write documentation for all SH options and add it to the
invoke.texi file. */
@@ -712,6 +716,7 @@ enum reg_class
T_REGS,
MAC_REGS,
FPUL_REGS,
+ SIBCALL_REGS,
GENERAL_REGS,
FP0_REGS,
FP_REGS,
@@ -733,6 +738,7 @@ enum reg_class
"T_REGS", \
"MAC_REGS", \
"FPUL_REGS", \
+ "SIBCALL_REGS", \
"GENERAL_REGS", \
"FP0_REGS", \
"FP_REGS", \
@@ -754,6 +760,8 @@ enum reg_class
{ 0x00040000, 0x00000000 }, /* T_REGS */ \
{ 0x00300000, 0x00000000 }, /* MAC_REGS */ \
{ 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
+ /* SIBCALL_REGS is initialized in CONDITIONAL_REGISTER_USAGE. */ \
+ { 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
{ 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \
{ 0x01000000, 0x00000000 }, /* FP0_REGS */ \
{ 0xFF000000, 0x000000FF }, /* FP_REGS */ \
Index: gcc/config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.md,v
retrieving revision 1.65
diff -u -p -r1.65 sh.md
--- gcc/config/sh/sh.md 2000/11/25 04:57:39 1.65
+++ gcc/config/sh/sh.md 2000/11/25 07:10:08
@@ -3408,7 +3408,7 @@
(use (reg:SI PIC_REG))
(clobber (reg:SI PR_REG))
(clobber (match_scratch:SI 2 "=r"))]
- "TARGET_SH2 && optimize"
+ "TARGET_SH2"
"#"
"reload_completed"
[(const_int 0)]
@@ -3467,7 +3467,7 @@
(use (reg:SI PIC_REG))
(clobber (reg:SI PR_REG))
(clobber (match_scratch:SI 3 "=r"))]
- "TARGET_SH2 && optimize"
+ "TARGET_SH2"
"#"
"reload_completed"
[(const_int 0)]
@@ -3497,7 +3497,7 @@
""
"
{
- if (flag_pic && TARGET_SH2 && optimize
+ if (flag_pic && TARGET_SH2
&& GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
{
@@ -3517,7 +3517,7 @@
""
"
{
- if (flag_pic && TARGET_SH2 && optimize
+ if (flag_pic && TARGET_SH2
&& GET_CODE (operands[1]) == MEM
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
{
@@ -3530,8 +3530,7 @@
}")
(define_insn "sibcalli"
- ;; FIXME: any call-clobbered register will do
- [(call (mem:SI (match_operand:SI 0 "register_operand" "z"))
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
(match_operand 1 "" ""))
(use (reg:PSI FPSCR_REG))
(return)]
@@ -3541,8 +3540,7 @@
(set_attr "type" "jump_ind")])
(define_insn "sibcalli_pcrel"
- ;; FIXME: any call-clobbered register will do
- [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "z"))
+ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
(use (reg:PSI FPSCR_REG))
@@ -3556,10 +3554,9 @@
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
(match_operand 1 "" ""))
(use (reg:PSI FPSCR_REG))
- ;; FIXME: any call-clobbered register will do
- (clobber (match_scratch:SI 2 "=z"))
+ (clobber (match_scratch:SI 2 "=k"))
(return)]
- "TARGET_SH2 && optimize"
+ "TARGET_SH2"
"#"
"reload_completed"
[(const_int 0)]
@@ -3584,7 +3581,7 @@
""
"
{
- if (flag_pic && TARGET_SH2 && optimize
+ if (flag_pic && TARGET_SH2
&& GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
/* The PLT needs the PIC register, but the epilogue would have
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist *Please* write to mailing lists, not to me