This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

Re: MMX/SSE patch: adding builtins


On Sun, 17 Sep 2000, Richard Henderson wrote:

> > +  target = gen_rtx_SUBREG (QImode, gen_reg_rtx (SImode), 0);
> > +
> > +  if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
> > +    op0 = copy_to_mode_reg (mode0, op0);
> > +  if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
> > +    op1 = copy_to_mode_reg (mode1, op1);
> > +
> > +  op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
> > +  pat = GEN_FCN (d->icode) (op0, op1, op2);
> > +  if (! pat)
> > +    return 0;
> > +  emit_insn (pat);
> > +  emit_insn (gen_setcc_2 (target, op2));
> 
> This isn't right.  You're using a set strict_low_part without
> first initializing the whole register.  
> 
> The rest appears ok.

Committed with the following fix.

Bernd

--- config/i386/i386.1.c	Mon Sep 18 10:43:17 2000
+++ config/i386/i386.c	Mon Sep 18 10:43:31 2000
@@ -7864,7 +7864,9 @@
       comparison = swap_condition (comparison);
     }
 
-  target = gen_rtx_SUBREG (QImode, gen_reg_rtx (SImode), 0);
+  target = gen_reg_rtx (SImode);
+  emit_move_insn (target, const0_rtx);
+  target = gen_rtx_SUBREG (QImode, target, 0);
 
   if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
     op0 = copy_to_mode_reg (mode0, op0);


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]