Another sh problem with fpul

[Bernd Schmidt <bernds at redhat dot co dot uk>]

When reload encounters a paradoxical subreg of the form
   (subreg:SI (mem:HI blah))
in the input of a floatsisf pattern, it tries to reload the mem into the
fpul register in HImode.  That mode isn't valid for fpul, so we get a spill
failure.

The simplest solution seems to be to disallow subregs in that position.  I've
borrowed some code from the alpha backend to do this.  This patch also changes
two unrelated patterns to use a slightly more correct predicate.


Bernd

	* sh.c (reg_no_subreg_operand): New function.
	* sh-protos.h (reg_no_subreg_operand): Declare it.
	* sh.h (PREDICATE_CODES): Add it.
	* sh.md (floatsisf2_i4, floatsidf2_i, extendsfdf2_i4): Use it for
	input operand that needs to be in fpul.
	(fix_truncsfsi2, fix_truncsfsi2_i4): Use register_operand for output.

Index: sh-protos.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh-protos.h,v
retrieving revision 1.9
diff -u -p -r1.9 sh-protos.h
--- sh-protos.h	2000/09/07 22:24:33	1.9
+++ sh-protos.h	2000/09/17 13:04:57
@@ -81,6 +81,7 @@ extern int system_reg_operand PARAMS ((r
 extern int general_movsrc_operand PARAMS ((rtx, enum machine_mode));
 extern int general_movdst_operand PARAMS ((rtx, enum machine_mode));
 extern int arith_reg_operand PARAMS ((rtx, enum machine_mode));
+extern int reg_no_subreg_operand PARAMS ((rtx, enum machine_mode));
 extern int fp_arith_reg_operand PARAMS ((rtx, enum machine_mode));
 extern int fp_extended_operand PARAMS ((rtx, enum machine_mode));
 extern int arith_operand PARAMS ((rtx, enum machine_mode));
Index: sh.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.c,v
retrieving revision 1.62
diff -u -p -r1.62 sh.c
--- sh.c	2000/09/07 22:24:33	1.62
+++ sh.c	2000/09/17 13:04:59
@@ -4629,6 +4629,20 @@ general_movdst_operand (op, mode)
   return general_operand (op, mode);
 }
 
+/* Accept a register, but not a subreg of any kind.  This allows us to
+   avoid pathological cases in reload wrt data movement common in 
+   int->fp conversion.  */
+
+int
+reg_no_subreg_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == SUBREG)
+    return 0;
+  return register_operand (op, mode);
+}
+
 /* Returns 1 if OP is a normal arithmetic register.  */
 
 int
Index: sh.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.h,v
retrieving revision 1.77
diff -u -p -r1.77 sh.h
--- sh.h	2000/09/15 16:33:52	1.77
+++ sh.h	2000/09/17 13:04:59
@@ -2231,6 +2231,7 @@ extern struct rtx_def *fpscr_rtx;
 #define PREDICATE_CODES \
   {"arith_operand", {SUBREG, REG, CONST_INT}},				\
   {"arith_reg_operand", {SUBREG, REG}},					\
+  {"reg_no_subreg_operand", {REG}},					\
   {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
   {"binary_float_operator", {PLUS, MULT}},				\
   {"commutative_float_operator", {PLUS, MULT}},				\
Index: sh.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.md,v
retrieving revision 1.48
diff -u -p -r1.48 sh.md
--- sh.md	2000/09/15 16:33:52	1.48
+++ sh.md	2000/09/17 13:05:00
@@ -4232,7 +4232,7 @@ else
 
 (define_insn "floatsisf2_i4"
   [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(float:SF (match_operand:SI 1 "register_operand" "y")))
+	(float:SF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH3E"
   "float	%1,%0"
@@ -4248,7 +4248,7 @@ else
 ;;  [(set_attr "type" "fp")])
 
 (define_expand "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=y")
+  [(set (match_operand:SI 0 "register_operand" "=y")
 	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
   "TARGET_SH3E"
   "
@@ -4261,7 +4261,7 @@ else
 }")
 
 (define_insn "fix_truncsfsi2_i4"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=y")
+  [(set (match_operand:SI 0 "register_operand" "=y")
 	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
@@ -4487,7 +4487,7 @@ else
 
 (define_insn "floatsidf2_i"
   [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(float:DF (match_operand:SI 1 "register_operand" "y")))
+	(float:DF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "float	%1,%0"
@@ -4631,7 +4631,7 @@ else
 
 (define_insn "extendsfdf2_i4"
   [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "y")))
+	(float_extend:DF (match_operand:SF 1 "reg_no_subreg_operand" "y")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "fcnvsd  %1,%0"