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Re: PATH: reorg.c improve optimize_skip (second try)

  In message <>you write:
  > Hello,
  > This is the second time I am trying to send this patch. Could some one
  > review this patch?
  > Text from last patch:
  > I generated some new code for reorg.c to handle targets with more than
  > 1 delay slot. Currently only the c4x (3 delay slots) has these. I know
  > some one who is working on the sharc port (2 delay slots) for gcc that
  > also uses these patches.
  > I optimized the routine optimize_skip to handle more than 1 delay slot.
  > The routine is only called for empty delay lists. We cannot generate
  > a skip insn if we allready have some delay insns in the delay list
  > because we could annul them.
  > We also do not return any insns from optimize_skip is we could not
  > find a skip. We do this because we only checked for annul_true/annul_false
  > and not for normal delay insns. Normal delay insns are prefered because
  > they allways execute in the delay list.
[ ... ]
  > 2000-07-31 Herman A.J. ten Brugge <>
  >         * reorg.c (optimize_skip) Handle targets with more than 1 delay slo
  > t.
There's no way this can be correct as far as I can tell.

It seems to me that if we fill multiple slots with annulled false branches,
then we can invert the jump multiple times.  At worst this is dead wrong,
at best the code is unreadable.

Assume we have 2 unfilled slots and that we manage to put 2 annul-false 
instructions in those delay slots, then we end up inverting the jump
twice.  Ugh.

At the very least you've got some very non-obvious flow control in this code
that needs to be untangled.


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