Re: cc register usage on i386/2.96

[Jan Hubicka <jh at suse dot cz>]

> On Fri, Sep 08, 2000 at 02:32:22PM +0200, Jan Hubicka wrote:
> > But thinks don't work as expected and the overflow bit is set incorrectly.
> > It seems to me, that overflow is not set properly even for add/sub
> > instructions and thus we should disable the CCmode version of the patterns...
> 
> How irritating.  The thing is, I can't figure why setg tests
> the overflow flag at all.  Why doesn't it test zf==0 && sf==0?
I was thinking about this a bit more and it seems to me, that we've just
missmodeled the instruction - it is not too broken.
> 
> Well, a similar test with subtract does seem to work, so you
> only need to diable CCmode add.
It don't work as well (I do have testcase somewhere), gcc believe that sub does
test a-b <-> 0, but it don't. If I understand it correctly, it is equivalent of
cmp instruction (from flag point of view) and does a <-> b.  So we should model
it as:
(set (op 0) (sub (op1) (op2))
(set (reg:CC CFLAGS) (compare (op1) (op2))

But I am not sure combine will be able to construct this - I believe it
has some logic to combine flags together with same operation.  I will try it
today.

The plus instruction IMO will produce correct results if we model it as
a <-> -b
(set (op 0) (plus (op1) (op2))
(set (reg:CC CFLAGS) (compare (op1) (neg (op2))))

Combine is able to produce the second and I believe that then we can allow
CCmode.  The real problem is, that carry/overflow bit is not set as after
subtracting result from 0, as we do model, but as natural for given operation.

I will try this today and check the documentation too.

Honza
> 
> 
> r~