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Re: choose_reload_regs V2.0


On Wed, 6 Sep 2000, Jeffrey A Law wrote:

>   > Patch #1:
>   > 	* mips.md (adddi3_internal_1): Make operand 3 an earlyclobber.
> Looks good to me.  I also suspect adddi3_internal_2, subdi3_internal,
> and subdi3_internal_2 need similar fixes.  There's also a number of
> define_splits which look suspicious.  negdi2_internal appears to be OK.

How about the patch below?  Note that it's untested; I'm having some problems
building mips targets with current CVS.

>   > Patch #2:
>   > 	* reload.c (regno_clobbered_p): Accept new arg, MODE, and use it
>   > 	to handle multiword modes correctly.  All callers and the declaration
>   > 	changed.
> Approved.

Installed.

Bernd

	* mips.md (adddi3, subdi3): Turn scratch operand into a match_scratch.
	All of the helper patterns and splitters changed accordingly.
	(adddi3_internal_1, adddi3_internal_2, subdi3_internal,
	subdi3_internal_2): Add earlyclobbers as appropriate.
	(some adddi3 splitters): Remove constraint strings.

Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.md,v
retrieving revision 1.84
diff -u -p -r1.84 mips.md
--- mips.md	2000/08/08 22:40:49	1.84
+++ mips.md	2000/09/07 09:56:10
@@ -688,7 +688,7 @@
   [(parallel [(set (match_operand:DI 0 "register_operand" "")
 		   (plus:DI (match_operand:DI 1 "se_register_operand" "")
 			    (match_operand:DI 2 "se_arith_operand" "")))
-	      (clobber (match_dup 3))])]
+	      (clobber (match_scratch:SI 3 ""))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
   "
 {
@@ -707,15 +707,13 @@
 					operands[2]));
       DONE;
     }
-
-  operands[3] = gen_reg_rtx (SImode);
 }")
 
 (define_insn "adddi3_internal_1"
   [(set (match_operand:DI 0 "register_operand" "=d,&d")
 	(plus:DI (match_operand:DI 1 "register_operand" "0,d")
 		 (match_operand:DI 2 "register_operand" "d,d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
+   (clobber (match_scratch:SI 3 "=&d,&d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
   "*
 {
@@ -732,7 +730,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -762,7 +760,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -792,7 +790,7 @@
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
 	(plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
 		 (match_operand:DI 2 "small_int" "P,J,N")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
+   (clobber (match_scratch:SI 3 "=&d,X,&d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && (TARGET_GAS
        || GET_CODE (operands[2]) != CONST_INT
@@ -809,7 +807,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -833,7 +831,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -1222,7 +1220,7 @@
   [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
 		   (minus:DI (match_operand:DI 1 "se_register_operand" "d")
 			     (match_operand:DI 2 "se_register_operand" "d")))
-	      (clobber (match_dup 3))])]
+	      (clobber (match_scratch:SI 3))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
   "
 {
@@ -1232,15 +1230,13 @@
 					operands[2]));
       DONE;
     }
-
-  operands[3] = gen_reg_rtx (SImode);
 }")
 
 (define_insn "subdi3_internal"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(minus:DI (match_operand:DI 1 "register_operand" "d")
 		  (match_operand:DI 2 "register_operand" "d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+   (clobber (match_scratch:SI 3 "=&d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
   "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
   [(set_attr "type"	"darith")
@@ -1251,7 +1247,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(minus:DI (match_operand:DI 1 "register_operand" "")
 		  (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -1279,7 +1275,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(minus:DI (match_operand:DI 1 "register_operand" "")
 		  (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -1307,7 +1303,7 @@
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
 	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
 		  (match_operand:DI 2 "small_int" "P,J,N")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
+   (clobber (match_scratch:SI 3 "=&d,X,&d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && INTVAL (operands[2]) != -32768"
   "@
@@ -1322,7 +1318,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(minus:DI (match_operand:DI 1 "register_operand" "")
 		  (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
@@ -1346,7 +1342,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(minus:DI (match_operand:DI 1 "register_operand" "")
 		  (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_scratch:SI 3 ""))]
   "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
    && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))


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