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Re: cr logical insn implementation for rs6000


	Given this recent change, I would like to refer back to my
proposed patch of about a month ago cleaning up some of the sCOND
patterns.  As far as I can tell, some of the patterns are better done by
GCC's portable code, especially when not on the POWER architecture.

	Also, the function unit information has a number of errors
following the addition of cr_logical attribute.  I also do not understand
why cr_logical instructions are assigned a latency of 4 cycles when they
all operate in 1 cycle.

	My patch below contains both the sCOND improvements and the cr
logical instruction unit rearrangement, but I did not change the latency
information until I hear whether 4 cycles was a typo or intended.

Thanks, David

	P.S. Geoff, in the future, please contact me for function unit
information.


Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.99
diff -c -p -r1.99 rs6000.md
*** rs6000.md	2000/09/06 09:12:51	1.99
--- rs6000.md	2000/09/06 17:58:49
***************
*** 125,131 ****
  
  (define_function_unit "iu" 1 0
    (and (eq_attr "type" "cr_logical")
!        (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601"))
    1 1)
  
  (define_function_unit "iu" 1 0
--- 125,131 ----
  
  (define_function_unit "iu" 1 0
    (and (eq_attr "type" "cr_logical")
!        (eq_attr "cpu" "mpccore,ppc403,ppc601"))
    1 1)
  
  (define_function_unit "iu" 1 0
***************
*** 353,359 ****
  ; fp compare uses fp unit
  (define_function_unit "fpu" 1 0
    (and (eq_attr "type" "fpcompare")
!        (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
    5 1)
  
  (define_function_unit "fpu" 1 0
--- 353,359 ----
  ; fp compare uses fp unit
  (define_function_unit "fpu" 1 0
    (and (eq_attr "type" "fpcompare")
!        (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
    5 1)
  
  (define_function_unit "fpu" 1 0
***************
*** 368,386 ****
  
  (define_function_unit "bpu" 1 0
    (and (eq_attr "type" "mtjmpr")
!        (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
    4 1)
  
  (define_function_unit "bpu" 1 0
    (and (eq_attr "type" "cr_logical")
!        (eq_attr "cpu" "ppc604,ppc620"))
    4 1)
    
  (define_function_unit "cru" 1 0
    (and (eq_attr "type" "cr_logical")
!        (eq_attr "cpu" "ppc604e"))
    4 1)
-   
  
  ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
  (define_function_unit "bpu" 1 0
--- 368,385 ----
  
  (define_function_unit "bpu" 1 0
    (and (eq_attr "type" "mtjmpr")
!        (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
    4 1)
  
  (define_function_unit "bpu" 1 0
    (and (eq_attr "type" "cr_logical")
!        (eq_attr "cpu" "rios1,rios2,ppc604"))
    4 1)
    
  (define_function_unit "cru" 1 0
    (and (eq_attr "type" "cr_logical")
!        (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
    4 1)
  
  ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
  (define_function_unit "bpu" 1 0
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 9988,9995 ****
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
    "
! { 
!   if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
      FAIL;
  
    rs6000_emit_sCOND (GT, operands[0]); 
--- 9987,9995 ----
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
    "
! {
!   if (! rs6000_compare_fp_p
!       && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
      FAIL;
  
    rs6000_emit_sCOND (GT, operands[0]); 
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10001,10026 ****
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
    "
! { 
!   if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
      FAIL;
  
    rs6000_emit_sCOND (LT, operands[0]); 
    DONE;
  }")
  
  (define_expand "sge"
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
!   "{ rs6000_emit_sCOND (GE, operands[0]); DONE; }")
  
  ;; A <= 0 is best done the portable way for A an integer.
  (define_expand "sle"
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
    "
! { 
!   if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
      FAIL;
  
    rs6000_emit_sCOND (LE, operands[0]); 
--- 10001,10037 ----
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
    "
! {
!   if (! rs6000_compare_fp_p 
!       && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
      FAIL;
  
    rs6000_emit_sCOND (LT, operands[0]); 
    DONE;
  }")
  
+ ;; A >= 0 is best done the portable way for A an integer.
  (define_expand "sge"
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
!   "
! {
!   if (! rs6000_compare_fp_p
!       && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
!     FAIL;
! 
!   rs6000_emit_sCOND (GE, operands[0]);
!   DONE;
! }")
  
  ;; A <= 0 is best done the portable way for A an integer.
  (define_expand "sle"
    [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
    ""
    "
! {
!   if (! rs6000_compare_fp_p
!       && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
      FAIL;
  
    rs6000_emit_sCOND (LE, operands[0]); 
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 11463,11484 ****
     [(set_attr "length" "12")])
  
  (define_insn ""
-   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- 	(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- 	       (const_int 0)))]
-   "! TARGET_POWER && ! TARGET_POWERPC64"
-   "nand %0,%1,%1\;{sri|srwi} %0,%0,31"
-    [(set_attr "length" "8")])
- 
- (define_insn ""
-   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- 	(ge:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- 	       (const_int 0)))]
-   "TARGET_POWERPC64"
-   "nand %0,%1,%1\;srdi %0,%0,63"
-    [(set_attr "length" "8")])
- 
- (define_insn ""
    [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
  	(compare:CC
  	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
--- 11474,11479 ----
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 11513,11580 ****
    "")
  
  (define_insn ""
-   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- 	(compare:CC
- 	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- 		(const_int 0))
- 	 (const_int 0)))
-    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- 	(ge:SI (match_dup 1) (const_int 0)))]
-   "! TARGET_POWER"
-   "@
-    nand %0,%1,%1\;{sri.|srwi.} %0,%0,31
-    #"
-   [(set_attr "type" "compare")
-    (set_attr "length" "8,12")])
- 
- (define_split
-   [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- 	(compare:CC
- 	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- 		(const_int 0))
- 	 (const_int 0)))
-    (set (match_operand:SI 0 "gpc_reg_operand" "")
- 	(ge:SI (match_dup 1) (const_int 0)))]
-   "! TARGET_POWER && reload_completed"
-   [(set (match_dup 0)
- 	(ge:SI (match_dup 1) (const_int 0)))
-    (set (match_dup 4)
- 	(compare:CC (match_dup 0)
- 		    (const_int 0)))]
-   "")
- 
- (define_insn ""
-   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- 	(compare:CC
- 	 (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- 		(const_int 0))
- 	 (const_int 0)))
-    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- 	(ge:DI (match_dup 1) (const_int 0)))]
-   "TARGET_POWERPC64"
-   "@
-    nand %0,%1,%1\;srdi. %0,%0,63
-    #"
-   [(set_attr "type" "compare")
-    (set_attr "length" "8,12")])
- 
- (define_split
-   [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- 	(compare:CC
- 	 (ge:DI (match_operand:DI 1 "gpc_reg_operand" "")
- 		(const_int 0))
- 	 (const_int 0)))
-    (set (match_operand:DI 0 "gpc_reg_operand" "")
- 	(ge:DI (match_dup 1) (const_int 0)))]
-   "TARGET_POWERPC64 && reload_completed"
-   [(set (match_dup 0)
- 	(ge:DI (match_dup 1) (const_int 0)))
-    (set (match_dup 4)
- 	(compare:CC (match_dup 0)
- 		    (const_int 0)))]
-   "")
- 
- (define_insn ""
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
  	(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
  			(match_operand:SI 2 "reg_or_short_operand" "rI"))
--- 11508,11513 ----
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 11659,11858 ****
    "TARGET_POWER"
    "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
    [(set_attr "length" "12")])
- 
- ;; This is (and (neg (ge X (const_int 0))) Y).
- ;; srawi sign-extends, so these patterrns are 64-bit safe.
- (define_insn ""
-   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- 	(and:SI (neg:SI
- 		 (lshiftrt:SI
- 		  (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- 		  (const_int 31)))
- 		(match_operand:SI 2 "gpc_reg_operand" "r")))
-    (clobber (match_scratch:SI 3 "=&r"))]
-   ""
-   "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
-   [(set_attr "length" "8")])
- 
- (define_insn ""
-   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- 	(and:DI (neg:DI
- 		 (lshiftrt:DI
- 		  (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
- 		  (const_int 63)))
- 		(match_operand:DI 2 "gpc_reg_operand" "r")))
-    (clobber (match_scratch:DI 3 "=&r"))]
-   "TARGET_POWERPC64"
-   "sradi %3,%1,63\;andc %0,%2,%3"
-   [(set_attr "length" "8")])
- 
- (define_insn ""
-   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- 	(compare:CC
- 	 (and:SI (neg:SI
- 		  (lshiftrt:SI
- 		   (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- 		   (const_int 31)))
- 		 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- 	 (const_int 0)))
-    (clobber (match_scratch:SI 3 "=&r,&r"))]
-   ""
-   "@
-    {srai|srawi} %3,%1,31\;andc. %3,%2,%3
-    #"
-   [(set_attr "type" "compare")
-    (set_attr "length" "8,12")])
- 
- (define_split
-   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- 	(compare:CC
- 	 (and:SI (neg:SI
- 		  (lshiftrt:SI
- 		   (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- 		   (const_int 31)))
- 		 (match_operand:SI 2 "gpc_reg_operand" ""))
- 	 (const_int 0)))
-    (clobber (match_scratch:SI 3 ""))]
-   "reload_completed"
-   [(set (match_dup 3)
- 	(and:SI (neg:SI (lshiftrt:SI
- 		   (not:SI (match_dup 1))
- 		   (const_int 31)))
- 		 (match_dup 2)))
-    (set (match_dup 0)
- 	(compare:CC (match_dup 3)
- 		    (const_int 0)))]
-   "")
- 
- (define_insn ""
-   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- 	(compare:CC
- 	 (and:DI (neg:DI
- 		  (lshiftrt:DI
- 		   (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- 		   (const_int 63)))
- 		 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- 	 (const_int 0)))
-    (clobber (match_scratch:DI 3 "=&r,&r"))]
-   "TARGET_POWERPC64"
-   "@
-    sradi %3,%1,63\;andc. %3,%2,%3
-    #"
-   [(set_attr "type" "compare")
-    (set_attr "length" "8,12")])
- 
- (define_split
-   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- 	(compare:CC
- 	 (and:DI (neg:DI
- 		  (lshiftrt:DI
- 		   (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- 		   (const_int 63)))
- 		 (match_operand:DI 2 "gpc_reg_operand" ""))
- 	 (const_int 0)))
-    (clobber (match_scratch:DI 3 ""))]
-   "TARGET_POWERPC64 && reload_completed"
-   [(set (match_dup 3)
- 	(and:DI (neg:DI (lshiftrt:DI
- 		   (not:DI (match_dup 1))
- 		   (const_int 63)))
- 		 (match_dup 2)))
-    (set (match_dup 0)
- 	(compare:CC (match_dup 3)
- 		    (const_int 0)))]
-   "")
- 
- (define_insn ""
-   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- 	(compare:CC
- 	 (and:SI (neg:SI
- 		  (lshiftrt:SI
- 		   (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- 		   (const_int 31)))
- 		 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- 	 (const_int 0)))
-    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- 	(and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
- 				     (const_int 31)))
- 		(match_dup 2)))
-    (clobber (match_scratch:SI 3 "=&r,&r"))]
-   ""
-   "@
-    {srai|srawi} %3,%1,31\;andc. %0,%2,%3
-    #"
-   [(set_attr "type" "compare")
-    (set_attr "length" "8,12")])
- 
- (define_split
-   [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- 	(compare:CC
- 	 (and:SI (neg:SI
- 		  (lshiftrt:SI
- 		   (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- 		   (const_int 31)))
- 		 (match_operand:SI 2 "gpc_reg_operand" ""))
- 	 (const_int 0)))
-    (set (match_operand:SI 0 "gpc_reg_operand" "")
- 	(and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
- 				     (const_int 31)))
- 		(match_dup 2)))
-    (clobber (match_scratch:SI 3 ""))]
-   "reload_completed"
-   [(parallel [(set (match_dup 0)
- 	(and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
- 				     (const_int 31)))
- 		(match_dup 2)))
-    (clobber (match_dup 3))])
-    (set (match_dup 4)
- 	(compare:CC (match_dup 0)
- 		    (const_int 0)))]
-   "")
- 
- (define_insn ""
-   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- 	(compare:CC
- 	 (and:DI (neg:DI
- 		  (lshiftrt:DI
- 		   (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- 		   (const_int 63)))
- 		 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- 	 (const_int 0)))
-    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- 	(and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
- 				     (const_int 63)))
- 		(match_dup 2)))
-    (clobber (match_scratch:SI 3 "=&r,&r"))]
-   "TARGET_POWERPC64"
-   "@
-    sradi %3,%1,63\;andc. %0,%2,%3
-    #"
-   [(set_attr "type" "compare")
-    (set_attr "length" "8,12")])
- 
- (define_split
-   [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- 	(compare:CC
- 	 (and:DI (neg:DI
- 		  (lshiftrt:DI
- 		   (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- 		   (const_int 63)))
- 		 (match_operand:DI 2 "gpc_reg_operand" ""))
- 	 (const_int 0)))
-    (set (match_operand:DI 0 "gpc_reg_operand" "")
- 	(and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
- 				     (const_int 63)))
- 		(match_dup 2)))
-    (clobber (match_scratch:SI 3 ""))]
-   "TARGET_POWERPC64 && reload_completed"
-   [(parallel [(set (match_dup 0)
- 	(and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
- 				     (const_int 63)))
- 		(match_dup 2)))
-    (clobber (match_dup 3))])
-    (set (match_dup 4)
- 	(compare:CC (match_dup 0)
- 		    (const_int 0)))]
-   "")
  
  (define_insn ""
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
--- 11592,11597 ----

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