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[RFC] PowerPC SCC cleanup
- To: gcc-patches at gcc dot gnu dot org
- Subject: [RFC] PowerPC SCC cleanup
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Fri, 11 Aug 2000 18:04:42 -0400
- cc: Geoff Keating <geoffk at cygnus dot com>
The rs6000 port SCC patterns were written a very long time ago and
have not been updated much. I have been trying to understand why certain
patterns were written the way they were. It looks like one may have
needed to create an SCC instruction at one point to get certain combiner
patterns to be recognized, but invoking FAIL for
(ge:SI (reg) (const_int 0))
doesn't seem to make any difference whether a combiner pattern is matched
with the current sources.
Without the POWER-arcihtecture "doz" instructions, many of the
optimizations are unavailable for PowerPC. From some experiments, the
portable code sequences for sgt, sge, slt, and sle seem to be fine for
PowerPC and provide better scheduling flexibility.
The following patch will bail out for sgt, sge, slt, and sge if
! TARGET_POWER. It also removes a number of superfluous combiner patterns:
x >= 0 for PowerPC (portable sequence is good) and a series of patterns
for
(and (neg (ge X (const_int 0))) Y)
which I cannot get GCC to generate under any circumstances. The latter
one is cute, although I do not know when it would be particularly useful.
Any objection to / comment on applying the following patch?
Should the SCC patterns instead be changed so that they never fail?
Thanks, David
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.97
diff -c -p -r1.97 rs6000.md
*** rs6000.md 2000/08/08 18:50:14 1.97
--- rs6000.md 2000/08/11 21:20:04
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10168,10174 ****
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
! if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
operands[1] = gen_rtx_COMPARE (mode,
--- 10168,10175 ----
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
! if (! rs6000_compare_fp_p
! && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
FAIL;
operands[1] = gen_rtx_COMPARE (mode,
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10197,10203 ****
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
! if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
operands[1] = gen_rtx_COMPARE (mode,
--- 10198,10205 ----
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
! if (! rs6000_compare_fp_p
! && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
FAIL;
operands[1] = gen_rtx_COMPARE (mode,
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10217,10222 ****
--- 10219,10225 ----
}
}")
+ ;; A >= 0 is best done the portable way for A an integer.
(define_expand "sge"
[(set (match_dup 2) (match_dup 1))
(set (match_operand:SI 0 "gpc_reg_operand" "")
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10224,10229 ****
--- 10227,10237 ----
""
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
+
+ if (! rs6000_compare_fp_p
+ && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
+ FAIL;
+
operands[1] = gen_rtx_COMPARE (mode,
rs6000_compare_op0, rs6000_compare_op1);
operands[2] = gen_reg_rtx (mode);
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10250,10256 ****
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
! if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
FAIL;
operands[1] = gen_rtx_COMPARE (mode,
--- 10258,10265 ----
"
{ enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
! if (! rs6000_compare_fp_p
! && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
FAIL;
operands[1] = gen_rtx_COMPARE (mode,
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 11818,11839 ****
[(set_attr "length" "12")])
(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 0)))]
- "! TARGET_POWER && ! TARGET_POWERPC64"
- "nand %0,%1,%1\;{sri|srwi} %0,%0,31"
- [(set_attr "length" "8")])
-
- (define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (const_int 0)))]
- "TARGET_POWERPC64"
- "nand %0,%1,%1\;srdi %0,%0,63"
- [(set_attr "length" "8")])
-
- (define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
(compare:CC
(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
--- 11827,11832 ----
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 11868,11935 ****
"")
(define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (const_int 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ge:SI (match_dup 1) (const_int 0)))]
- "! TARGET_POWER"
- "@
- nand %0,%1,%1\;{sri.|srwi.} %0,%0,31
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
- (define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (const_int 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ge:SI (match_dup 1) (const_int 0)))]
- "! TARGET_POWER && reload_completed"
- [(set (match_dup 0)
- (ge:SI (match_dup 1) (const_int 0)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
- (define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (const_int 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ge:DI (match_dup 1) (const_int 0)))]
- "TARGET_POWERPC64"
- "@
- nand %0,%1,%1\;srdi. %0,%0,63
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
- (define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (ge:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (const_int 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (ge:DI (match_dup 1) (const_int 0)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ge:DI (match_dup 1) (const_int 0)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
- (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
--- 11861,11866 ----
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 12014,12213 ****
"TARGET_POWER"
"doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")])
-
- ;; This is (and (neg (ge X (const_int 0))) Y).
- ;; srawi sign-extends, so these patterrns are 64-bit safe.
- (define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (and:SI (neg:SI
- (lshiftrt:SI
- (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (const_int 31)))
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=&r"))]
- ""
- "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
- [(set_attr "length" "8")])
-
- (define_insn ""
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (and:DI (neg:DI
- (lshiftrt:DI
- (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (const_int 63)))
- (match_operand:DI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:DI 3 "=&r"))]
- "TARGET_POWERPC64"
- "sradi %3,%1,63\;andc %0,%2,%3"
- [(set_attr "length" "8")])
-
- (define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:SI (neg:SI
- (lshiftrt:SI
- (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (const_int 31)))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- ""
- "@
- {srai|srawi} %3,%1,31\;andc. %3,%2,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (and:SI (neg:SI
- (lshiftrt:SI
- (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (const_int 31)))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "reload_completed"
- [(set (match_dup 3)
- (and:SI (neg:SI (lshiftrt:SI
- (not:SI (match_dup 1))
- (const_int 31)))
- (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
- (define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:DI (neg:DI
- (lshiftrt:DI
- (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (const_int 63)))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=&r,&r"))]
- "TARGET_POWERPC64"
- "@
- sradi %3,%1,63\;andc. %3,%2,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
- (define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (and:DI (neg:DI
- (lshiftrt:DI
- (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (const_int 63)))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (and:DI (neg:DI (lshiftrt:DI
- (not:DI (match_dup 1))
- (const_int 63)))
- (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
- (define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:SI (neg:SI
- (lshiftrt:SI
- (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (const_int 31)))
- (match_operand:SI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
- (const_int 31)))
- (match_dup 2)))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- ""
- "@
- {srai|srawi} %3,%1,31\;andc. %0,%2,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
- (define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (and:SI (neg:SI
- (lshiftrt:SI
- (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
- (const_int 31)))
- (match_operand:SI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
- (const_int 31)))
- (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 0)
- (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
- (const_int 31)))
- (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
- (define_insn ""
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC
- (and:DI (neg:DI
- (lshiftrt:DI
- (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
- (const_int 63)))
- (match_operand:DI 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
- (const_int 63)))
- (match_dup 2)))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_POWERPC64"
- "@
- sradi %3,%1,63\;andc. %0,%2,%3
- #"
- [(set_attr "type" "compare")
- (set_attr "length" "8,12")])
-
- (define_split
- [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
- (compare:CC
- (and:DI (neg:DI
- (lshiftrt:DI
- (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
- (const_int 63)))
- (match_operand:DI 2 "gpc_reg_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
- (const_int 63)))
- (match_dup 2)))
- (clobber (match_scratch:SI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(parallel [(set (match_dup 0)
- (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
- (const_int 63)))
- (match_dup 2)))
- (clobber (match_dup 3))])
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
--- 11945,11950 ----