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Re: config/h8300/h8300.md: Add a new peephole optimization.
- To: Kazu Hirata <kazu at hxi dot com>
- Subject: Re: config/h8300/h8300.md: Add a new peephole optimization.
- From: Jeffrey A Law <law at cygnus dot com>
- Date: Mon, 17 Jul 2000 03:02:12 -0600
- cc: gcc-patches at gcc dot gnu dot org
- Reply-To: law at cygnus dot com
In message <200007140607.XAA06423@cygnus.com>you write:
> Hi,
>
> Attached is a patch to add a new peephole optimization to the h8300
> target.
>
> It combines an increment/decrement insn (adds #1, r0) and a test insn
> (done by mov.w r0, r0) and emits inc.w r0. QI, HI, and SI modes are
> covered.
Understood.
> The reason I used a peephole instead of changing the existing
> (define_insn "addxx" ...) is that the target has used up all the
> constraint letters for interger constants. In order to implement
> this, I needed a letter representing integer constants, -1 and -2, so
> that I can use it for dec.[wl].
Can't you use Q, R, S, or T and have them match the proper constants?
Just because something is a constant dosn't mean you can't match it with
one of the generic backend constraints.
> mov.[bwl] clears the overflow bit in cc0 regardless of operands. The
> inc/dec insn does set the overflow bit if an overflow occurs and
> clears it if not. We can ignore this difference because the overflow
> bit is never used by gcc. All other cc0 bits work identically. Both
> mov and inc/dec set the negative flag and the zero flag properly.
Understood.
jeff