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Fix to alpha_align_insns
- To: gcc-patches at gcc dot gnu dot org
- Subject: Fix to alpha_align_insns
- From: kenner at vlsi1 dot ultra dot nyu dot edu (Richard Kenner)
- Date: Tue, 23 May 00 07:05:25 EDT
Tue May 23 06:50:29 2000 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
* config/alpha/alpha.c: Remove #ifdef HAIFA since now only scheduler.
(alpha_start_function): Never write ..ng label if VMS or NT.
(alpha_align_insns): Remove GP_IN_USE arg.
Alignment now unsigned.
(alpha_reorg): Don't pass GP_IN_USE arg to alpha_align_insns.
* config/alpha/alpha.md (prologue_ldgp): Split into one define_expand
and two define_insn's.
*** config/alpha/alpha.c 2000/05/23 01:44:05 1.129
--- config/alpha/alpha.c 2000/05/23 10:28:45
*************** alpha_start_function (file, fnname, decl
*** 4435,4439 ****
/* If the function needs GP, we'll write the "..ng" label there.
Otherwise, do it here. */
! if (! alpha_function_needs_gp)
{
putc ('$', file);
--- 4435,4440 ----
/* If the function needs GP, we'll write the "..ng" label there.
Otherwise, do it here. */
! if (! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT
! && ! alpha_function_needs_gp)
{
putc ('$', file);
*************** alpha_handle_trap_shadows (insns)
*** 5180,5184 ****
}
- #ifdef HAIFA
/* Alpha can only issue instruction groups simultaneously if they are
suitibly aligned. This is very processor-specific. */
--- 5181,5184 ----
*************** enum alphaev5_pipe {
*** 5204,5214 ****
static enum alphaev4_pipe alphaev4_insn_pipe PARAMS ((rtx));
static enum alphaev5_pipe alphaev5_insn_pipe PARAMS ((rtx));
! static rtx alphaev4_next_group PARAMS ((rtx, int*, int*));
! static rtx alphaev5_next_group PARAMS ((rtx, int*, int*));
! static rtx alphaev4_next_nop PARAMS ((int*));
! static rtx alphaev5_next_nop PARAMS ((int*));
static void alpha_align_insns
! PARAMS ((rtx, int, rtx (*)(rtx, int*, int*), rtx (*)(int*), int));
static enum alphaev4_pipe
--- 5204,5214 ----
static enum alphaev4_pipe alphaev4_insn_pipe PARAMS ((rtx));
static enum alphaev5_pipe alphaev5_insn_pipe PARAMS ((rtx));
! static rtx alphaev4_next_group PARAMS ((rtx, int *, int *));
! static rtx alphaev5_next_group PARAMS ((rtx, int *, int *));
! static rtx alphaev4_next_nop PARAMS ((int *));
! static rtx alphaev5_next_nop PARAMS ((int *));
static void alpha_align_insns
! PARAMS ((rtx, unsigned int, rtx (*)(rtx, int *, int *), rtx (*)(int *)));
static enum alphaev4_pipe
*************** alphaev4_insn_pipe (insn)
*** 5250,5254 ****
default:
! abort();
}
}
--- 5250,5254 ----
default:
! abort ();
}
}
*************** alphaev5_next_nop (pin_use)
*** 5597,5609 ****
static void
! alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
rtx insns;
! int max_align;
! rtx (*next_group) PARAMS ((rtx, int*, int*));
! rtx (*next_nop) PARAMS ((int*));
! int gp_in_use;
{
/* ALIGN is the known alignment for the insn group. */
! int align;
/* OFS is the offset of the current insn in the insn group. */
int ofs;
--- 5597,5608 ----
static void
! alpha_align_insns (insns, max_align, next_group, next_nop)
rtx insns;
! unsigned int max_align;
! rtx (*next_group) PARAMS ((rtx, int *, int *));
! rtx (*next_nop) PARAMS ((int *));
{
/* ALIGN is the known alignment for the insn group. */
! unsigned int align;
/* OFS is the offset of the current insn in the insn group. */
int ofs;
*************** alpha_align_insns (insns, max_align, nex
*** 5614,5629 ****
shorten_branches (insns);
! align = (FUNCTION_BOUNDARY/BITS_PER_UNIT < max_align
! ? FUNCTION_BOUNDARY/BITS_PER_UNIT : max_align);
- /* Account for the initial GP load, which happens before the scheduled
- prologue we emitted as RTL. */
ofs = prev_in_use = 0;
- if (alpha_does_function_need_gp())
- {
- ofs = 8 & (align - 1);
- prev_in_use = gp_in_use;
- }
-
i = insns;
if (GET_CODE (i) == NOTE)
--- 5613,5620 ----
shorten_branches (insns);
! align = (FUNCTION_BOUNDARY / BITS_PER_UNIT < max_align
! ? FUNCTION_BOUNDARY / BITS_PER_UNIT : max_align);
ofs = prev_in_use = 0;
i = insns;
if (GET_CODE (i) == NOTE)
*************** alpha_align_insns (insns, max_align, nex
*** 5632,5641 ****
while (i)
{
! next = (*next_group)(i, &in_use, &len);
/* When we see a label, resync alignment etc. */
if (GET_CODE (i) == CODE_LABEL)
{
! int new_align = 1 << label_to_alignment (i);
if (new_align >= align)
{
--- 5623,5633 ----
while (i)
{
! next = (*next_group) (i, &in_use, &len);
/* When we see a label, resync alignment etc. */
if (GET_CODE (i) == CODE_LABEL)
{
! unsigned int new_align = 1 << label_to_alignment (i);
!
if (new_align >= align)
{
*************** alpha_align_insns (insns, max_align, nex
*** 5643,5646 ****
--- 5635,5639 ----
ofs = 0;
}
+
else if (ofs & (new_align-1))
ofs = (ofs | (new_align-1)) + 1;
*************** alpha_align_insns (insns, max_align, nex
*** 5667,5671 ****
else if (align < len)
{
! int new_log_align = len > 8 ? 4 : 3;
rtx where;
--- 5660,5664 ----
else if (align < len)
{
! unsigned int new_log_align = len > 8 ? 4 : 3;
rtx where;
*************** alpha_align_insns (insns, max_align, nex
*** 5718,5722 ****
}
}
- #endif /* HAIFA */
/* Machine dependant reorg pass. */
--- 5711,5714 ----
*************** alpha_reorg (insns)
*** 5729,5736 ****
alpha_handle_trap_shadows (insns);
- #ifdef HAIFA
/* Due to the number of extra trapb insns, don't bother fixing up
alignment when trap precision is instruction. Moreover, we can
! only do our job when sched2 is run and Haifa is our scheduler. */
if (optimize && !optimize_size
&& alpha_tp != ALPHA_TP_INSN
--- 5721,5727 ----
alpha_handle_trap_shadows (insns);
/* Due to the number of extra trapb insns, don't bother fixing up
alignment when trap precision is instruction. Moreover, we can
! only do our job when sched2 is run. */
if (optimize && !optimize_size
&& alpha_tp != ALPHA_TP_INSN
*************** alpha_reorg (insns)
*** 5738,5750 ****
{
if (alpha_cpu == PROCESSOR_EV4)
! alpha_align_insns (insns, 8, alphaev4_next_group,
! alphaev4_next_nop, EV4_IB0);
else if (alpha_cpu == PROCESSOR_EV5)
! alpha_align_insns (insns, 16, alphaev5_next_group,
! alphaev5_next_nop, EV5_E01 | EV5_E0);
}
- #endif
}
-
/* Check a floating-point value for validity for a particular machine mode. */
--- 5729,5737 ----
{
if (alpha_cpu == PROCESSOR_EV4)
! alpha_align_insns (insns, 8, alphaev4_next_group, alphaev4_next_nop);
else if (alpha_cpu == PROCESSOR_EV5)
! alpha_align_insns (insns, 16, alphaev5_next_group, alphaev5_next_nop);
}
}
/* Check a floating-point value for validity for a particular machine mode. */
*** config/alpha/alpha.md 2000/05/23 01:44:05 1.117
--- config/alpha/alpha.md 2000/05/23 10:28:54
***************
*** 5494,5502 ****
}")
! (define_insn "prologue_ldgp"
! [(unspec_volatile [(const_int 0)] 9)]
""
"ldgp $29,0($27)\\n$%~..ng:")
(define_insn "init_fp"
[(set (match_operand:DI 0 "register_operand" "=r")
--- 5494,5520 ----
}")
! ;; These take care of emitting the ldgp insn in the prologue. This will be
! ;; an lda/ldah pair and we want to align them properly. So we have two
! ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
! ;; and the second of which emits nothing. However, both are marked as type
! ;; IADD (the default) so the alignment code in alpha.c does the right thing
! ;; with them.
!
! (define_expand "prologue_ldgp"
! [(unspec_volatile [(const_int 0)] 9)
! (unspec_volatile [(const_int 0)] 10)]
""
+ "")
+
+ (define_insn "*prologue_ldgp_1"
+ [(unspec_volatile [(const_int 0)] 9)]
+ "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
"ldgp $29,0($27)\\n$%~..ng:")
+ (define_insn "*prologue_ldgp_2"
+ [(unspec_volatile [(const_int 0)] 10)]
+ "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
+ "")
+
(define_insn "init_fp"
[(set (match_operand:DI 0 "register_operand" "=r")
***************
*** 5509,5518 ****
[(return)]
""
! "alpha_expand_epilogue ();")
(define_expand "sibcall_epilogue"
[(return)]
"!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
! "alpha_expand_epilogue (); DONE;")
(define_expand "eh_epilogue"
--- 5527,5543 ----
[(return)]
""
! "
! {
! alpha_expand_epilogue ();
! }")
(define_expand "sibcall_epilogue"
[(return)]
"!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
! "
! {
! alpha_expand_epilogue ();
! DONE;
! }")
(define_expand "eh_epilogue"
Index: fixinc/gnu-regex.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/fixinc/gnu-regex.h,v
retrieving revision 1.3
diff -c -2 -p -r1.3 gnu-regex.h
*** gnu-regex.h 2000/01/20 18:25:12 1.3
--- gnu-regex.h 2000/05/23 10:28:59
*************** extern reg_syntax_t re_syntax_options;
*** 282,288 ****
typedef enum
{
- #if (_XOPEN_SOURCE - 0) == 500
- REG_NOSYS = -1, /* This will never happen for this implementation. */
- #endif
REG_NOERROR = 0, /* Success. */
--- 282,285 ----