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minor ia64.md patch
- To: gcc-patches at gcc dot gnu dot org
- Subject: minor ia64.md patch
- From: Jim Wilson <wilson at cygnus dot com>
- Date: Wed, 10 May 2000 21:41:57 -0700
This just adds a little comment to explain the choice of instructions
generated by the insv pattern.
Wed May 10 21:31:44 2000 Jim Wilson <wilson@cygnus.com>
* config/ia64/ia64.md (insv): Add comment.
Index: ia64.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ia64/ia64.md,v
retrieving revision 1.12
diff -p -r1.12 ia64.md
*** ia64.md 2000/05/09 06:17:35 1.12
--- ia64.md 2000/05/11 04:30:25
***************
*** 684,689 ****
--- 684,704 ----
DONE;
}
+ /* We could handle remaining cases by emitting multiple dep
+ instructions.
+
+ If we need more than two dep instructions then we lose. A 6
+ insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
+ mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
+ the latter is 6 cycles on an Itanium (TM) processor, because there is
+ only one function unit that can execute dep and shr immed.
+
+ If we only need two dep instruction, then we still lose.
+ mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
+ the unnecessary mov, this is still undesirable because it will be
+ hard to optimize, and it creates unnecessary pressure on the I0
+ function unit. */
+
FAIL;
#if 0