This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: patch for case 102820
- To: Jeffrey A Law <law at cygnus dot com>
- Subject: Re: patch for case 102820
- From: Chandra Chavva <cchavva at cygnus dot com>
- Date: Thu, 17 Feb 2000 13:03:48 -0800 (PST)
- cc: gcc-patches at gcc dot gnu dot org
On Wed, 16 Feb 2000, Jeffrey A Law wrote:
> In message <Pine.SOL.3.91.1000215170531.25073b-100000@canuck.cygnus.com>you w
> rite:
> > Hi,
> >
> > I am working on a branch vr4xxxx of mips architecture, but in the CR
> > they mentioned problem in eCos.
> >
> > The customer is complaining about bc1* instructions. These instructions
> > should be separated by alteast one instruction from the preceding
> > floating point compare instruction.
> >
> > When i looked at the manual Vr4300 Microprocessor User's Manual for bc1f
> > and bc1t instruction, both have the following defination.
> >
> > The result of the comparison is sampled while the instruction
> > immediately preceding is executed, at least one instruciton must be
> > inserted in between the floating point compare instruction and this
> > instruction.
> >
> >
> > Since bc1* insn are generated immediately after the compare instructions
> > i have added a nop just before generating bc1f and bc1t insns.
> >
> > Here is the patch for this fix. Please let me know if this is fine.
> >
> > While debugging this code, i figured out we already have some in mips.c
> > which basically inserts nop before bc1* instructions. Who ever is owning
> > please let me know is this the right place to fix this bug or my fix is
> > fine.
> Addition of NOPs for MIPS ports without cpu interlocks is handled in the
> assembler, not the compiler. SO the proper place to fix this is in the
> assembler.
>
> jeff
>
bc1* instruction is a special instruction which does not have
interlocks. What is happening is, in the mips.md file the following
format is used to generate bc1* instructions:
mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" :
\"%*bc1f%?\\t%Z0%2\";
Here '*' means turn on both .set noreorder and .set nomacro if
filling delay slots. And .set noreorder directive doesnot reorder the
code and does not generate a nop insn.
I have changed '*' to '#' which says print nop if in a .set
noreorder section. And this generates a nop insn.
Please let me know if my fix is correct or not.
Thanks
Chandra
*config/mips/mips.md (branch_fp_ne): Changed the format of bc1*
to print nop.
(branch_fp_eq): Likewise
Index: mips.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/mips/mips.md,v
retrieving revision 1.151.6.4
diff -p -r1.151.6.4 mips.md
*** mips.md 1999/03/12 15:45:12 1.151.6.4
--- mips.md 2000/02/17 20:57:44
*************** move\\t%0,%z4\\n\\
*** 7858,7864 ****
"*
{
mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
! return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\";
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
--- 7858,7864 ----
"*
{
mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
! return (operands[1] != pc_rtx) ? \"%#bc1t%?\\t%Z0%1\" : \"%#bc1f%?\\t%Z0%2\";
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
*************** move\\t%0,%z4\\n\\
*** 7874,7880 ****
"*
{
mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
! return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\";
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
--- 7874,7880 ----
"*
{
mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
! return (operands[1] != pc_rtx) ? \"%#bc1f%?\\t%Z0%1\" : \"%#bc1t%?\\t%Z0%2\";
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")