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Re: g77-20000131 crash with -O2 -funroll-loops -mcpu=v8 on sparc
- To: Dan Nicolaescu <dann at ics dot uci dot edu>
- Subject: Re: g77-20000131 crash with -O2 -funroll-loops -mcpu=v8 on sparc
- From: Richard Henderson <rth at cygnus dot com>
- Date: Tue, 1 Feb 2000 19:04:30 -0800
- Cc: gcc-bugs at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- References: <200002011104.aa08769@gremlin-relay.ics.uci.edu> <20000201145817.A8262@cygnus.com> <200002011827.aa11625@gremlin-relay.ics.uci.edu>
On Tue, Feb 01, 2000 at 06:27:02PM -0800, Dan Nicolaescu wrote:
> Bootstraped on a solaris 2.5.1 machine. It still crashes.
Curious. Anyway, I had a look at the actual source and it's
pretty obvious what the problem is -- not checking for CONST_DOUBLE
before trying to turn it into a real.
But we can do better than merely fixing that bug.
r~
* sparc.c (fp_zero_operand): Turn into a normal predicate.
Use CONST0_RTX. Update all callers.
* sparc.h, sparc-protos.h: Update accordingly.
* sparc.md (fp mov insns): Use fp_zero_operand directly
where applicable.
Index: sparc-protos.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc-protos.h,v
retrieving revision 1.7
diff -c -p -d -r1.7 sparc-protos.h
*** sparc-protos.h 2000/01/25 12:42:25 1.7
--- sparc-protos.h 2000/02/02 02:59:42
*************** extern int eligible_for_return_delay PAR
*** 124,130 ****
extern int emit_move_sequence PARAMS ((rtx, enum machine_mode));
extern int extend_op PARAMS ((rtx, enum machine_mode));
extern int fcc_reg_operand PARAMS ((rtx, enum machine_mode));
! extern int fp_zero_operand PARAMS ((rtx));
extern int fp_sethi_p PARAMS ((rtx));
extern int fp_mov_p PARAMS ((rtx));
extern int fp_high_losum_p PARAMS ((rtx));
--- 124,130 ----
extern int emit_move_sequence PARAMS ((rtx, enum machine_mode));
extern int extend_op PARAMS ((rtx, enum machine_mode));
extern int fcc_reg_operand PARAMS ((rtx, enum machine_mode));
! extern int fp_zero_operand PARAMS ((rtx, enum machine_mode));
extern int fp_sethi_p PARAMS ((rtx));
extern int fp_mov_p PARAMS ((rtx));
extern int fp_high_losum_p PARAMS ((rtx));
Index: sparc.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.c,v
retrieving revision 1.109
diff -c -p -d -r1.109 sparc.c
*** sparc.c 2000/01/26 20:14:10 1.109
--- sparc.c 2000/02/02 02:59:42
*************** reg_or_0_operand (op, mode)
*** 387,395 ****
&& CONST_DOUBLE_HIGH (op) == 0
&& CONST_DOUBLE_LOW (op) == 0)
return 1;
! if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
! && GET_CODE (op) == CONST_DOUBLE
! && fp_zero_operand (op))
return 1;
return 0;
}
--- 387,393 ----
&& CONST_DOUBLE_HIGH (op) == 0
&& CONST_DOUBLE_LOW (op) == 0)
return 1;
! if (fp_zero_operand (op, mode))
return 1;
return 0;
}
*************** reg_or_0_operand (op, mode)
*** 397,409 ****
/* Nonzero if OP is a floating point value with value 0.0. */
int
! fp_zero_operand (op)
rtx op;
{
! REAL_VALUE_TYPE r;
!
! REAL_VALUE_FROM_CONST_DOUBLE (r, op);
! return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
}
/* Nonzero if OP is a floating point constant which can
--- 395,407 ----
/* Nonzero if OP is a floating point value with value 0.0. */
int
! fp_zero_operand (op, mode)
rtx op;
+ enum machine_mode mode;
{
! if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
! return 0;
! return op == CONST0_RTX (mode);
}
/* Nonzero if OP is a floating point constant which can
Index: sparc.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.h,v
retrieving revision 1.99
diff -c -p -d -r1.99 sparc.h
*** sparc.h 2000/01/26 02:06:20 1.99
--- sparc.h 2000/02/02 02:59:42
*************** extern char leaf_reg_remap[];
*** 1467,1474 ****
Here VALUE is the CONST_DOUBLE rtx itself. */
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
! ((C) == 'G' ? fp_zero_operand (VALUE) \
! : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
: 0)
/* Given an rtx X being reloaded into a reg required to be
--- 1467,1474 ----
Here VALUE is the CONST_DOUBLE rtx itself. */
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
! ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
! : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
: 0)
/* Given an rtx X being reloaded into a reg required to be
*************** LFLGRET"ID":\n\
*** 2266,2272 ****
(TARGET_VIS && \
(GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
GET_MODE (X) == TFmode) && \
! fp_zero_operand (X)))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
--- 2266,2272 ----
(TARGET_VIS && \
(GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
GET_MODE (X) == TFmode) && \
! fp_zero_operand (X, GET_MODE (X))))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
Index: sparc.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.99
diff -c -p -d -r1.99 sparc.md
*** sparc.md 2000/01/26 20:14:10 1.99
--- sparc.md 2000/02/02 02:59:43
***************
*** 3023,3029 ****
"(TARGET_FPU && ! TARGET_VIS && ! TARGET_LIVE_G0)
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode)
! || fp_zero_operand (operands[1]))"
"*
{
if (GET_CODE (operands[1]) == CONST_DOUBLE
--- 3023,3029 ----
"(TARGET_FPU && ! TARGET_VIS && ! TARGET_LIVE_G0)
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode)
! || fp_zero_operand (operands[1], SFmode))"
"*
{
if (GET_CODE (operands[1]) == CONST_DOUBLE
***************
*** 3068,3074 ****
"(TARGET_FPU && TARGET_VIS)
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode)
! || fp_zero_operand (operands[1]))"
"*
{
if (GET_CODE (operands[1]) == CONST_DOUBLE
--- 3068,3074 ----
"(TARGET_FPU && TARGET_VIS)
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode)
! || fp_zero_operand (operands[1], SFmode))"
"*
{
if (GET_CODE (operands[1]) == CONST_DOUBLE
***************
*** 3181,3189 ****
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
! if (TARGET_VIS
! && GET_CODE (operands[1]) == CONST_DOUBLE
! && fp_zero_operand (operands[1]))
goto movsf_is_ok;
/* emit_group_store will send such bogosity to us when it is
--- 3181,3187 ----
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
! if (TARGET_VIS && fp_zero_operand (operands[1], SFmode))
goto movsf_is_ok;
/* emit_group_store will send such bogosity to us when it is
***************
*** 3199,3207 ****
if (GET_CODE (operands[0]) == MEM)
{
if (register_operand (operands[1], SFmode)
! || (! TARGET_LIVE_G0
! && GET_CODE (operands[1]) == CONST_DOUBLE
! && fp_zero_operand (operands[1])))
goto movsf_is_ok;
if (! reload_in_progress)
--- 3197,3203 ----
if (GET_CODE (operands[0]) == MEM)
{
if (register_operand (operands[1], SFmode)
! || (! TARGET_LIVE_G0 && fp_zero_operand (operands[1], SFmode)))
goto movsf_is_ok;
if (! reload_in_progress)
***************
*** 3234,3252 ****
(define_insn "*clear_df"
[(set (match_operand:DF 0 "register_operand" "=e")
! (match_operand:DF 1 "const_double_operand" ""))]
! "TARGET_VIS
! && fp_zero_operand (operands[1])"
"fzero\\t%0"
[(set_attr "type" "fpmove")
(set_attr "length" "1")])
(define_insn "*clear_dfp"
[(set (match_operand:DF 0 "memory_operand" "=m")
! (match_operand:DF 1 "const_double_operand" ""))]
! "! TARGET_LIVE_G0
! && TARGET_V9
! && fp_zero_operand (operands[1])"
"stx\\t%%g0, %0"
[(set_attr "type" "store")
(set_attr "length" "1")])
--- 3230,3245 ----
(define_insn "*clear_df"
[(set (match_operand:DF 0 "register_operand" "=e")
! (match_operand:DF 1 "fp_zero_operand" ""))]
! "TARGET_VIS"
"fzero\\t%0"
[(set_attr "type" "fpmove")
(set_attr "length" "1")])
(define_insn "*clear_dfp"
[(set (match_operand:DF 0 "memory_operand" "=m")
! (match_operand:DF 1 "fp_zero_operand" ""))]
! "! TARGET_LIVE_G0 && TARGET_V9"
"stx\\t%%g0, %0"
[(set_attr "type" "store")
(set_attr "length" "1")])
***************
*** 3340,3348 ****
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
! if (TARGET_VIS
! && GET_CODE (operands[1]) == CONST_DOUBLE
! && fp_zero_operand (operands[1]))
goto movdf_is_ok;
/* emit_group_store will send such bogosity to us when it is
--- 3333,3339 ----
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
! if (TARGET_VIS && fp_zero_operand (operands[1], DFmode))
goto movdf_is_ok;
/* emit_group_store will send such bogosity to us when it is
***************
*** 3604,3621 ****
(define_insn "*clear_tf"
[(set (match_operand:TF 0 "register_operand" "=e")
! (match_operand:TF 1 "const_double_operand" ""))]
! "TARGET_VIS
! && fp_zero_operand (operands[1])"
"#"
[(set_attr "type" "fpmove")
(set_attr "length" "2")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
! (match_operand:TF 1 "const_double_operand" ""))]
! "TARGET_VIS && reload_completed
! && fp_zero_operand (operands[1])"
[(set (subreg:DF (match_dup 0) 0) (match_dup 1))
(set (subreg:DF (match_dup 0) 8) (match_dup 1))]
"
--- 3595,3610 ----
(define_insn "*clear_tf"
[(set (match_operand:TF 0 "register_operand" "=e")
! (match_operand:TF 1 "fp_zero_operand" ""))]
! "TARGET_VIS"
"#"
[(set_attr "type" "fpmove")
(set_attr "length" "2")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
! (match_operand:TF 1 "fp_zero_operand" ""))]
! "TARGET_VIS && reload_completed"
[(set (subreg:DF (match_dup 0) 0) (match_dup 1))
(set (subreg:DF (match_dup 0) 8) (match_dup 1))]
"
***************
*** 3626,3645 ****
(define_insn "*clear_tfp"
[(set (match_operand:TF 0 "memory_operand" "=m")
! (match_operand:TF 1 "const_double_operand" ""))]
! "! TARGET_LIVE_G0
! && TARGET_V9
! && fp_zero_operand (operands[1])"
"#"
[(set_attr "type" "fpmove")
(set_attr "length" "2")])
(define_split
[(set (match_operand:TF 0 "memory_operand" "=m")
! (match_operand:TF 1 "const_double_operand" ""))]
! "! TARGET_LIVE_G0
! && TARGET_V9 && reload_completed
! && fp_zero_operand (operands[1])"
[(set (subreg:DF (match_dup 0) 0) (match_dup 1))
(set (subreg:DF (match_dup 0) 8) (match_dup 1))]
"
--- 3615,3630 ----
(define_insn "*clear_tfp"
[(set (match_operand:TF 0 "memory_operand" "=m")
! (match_operand:TF 1 "fp_zero_operand" ""))]
! "! TARGET_LIVE_G0 && TARGET_V9"
"#"
[(set_attr "type" "fpmove")
(set_attr "length" "2")])
(define_split
[(set (match_operand:TF 0 "memory_operand" "=m")
! (match_operand:TF 1 "fp_zero_operand" ""))]
! "! TARGET_LIVE_G0 && TARGET_V9 && reload_completed"
[(set (subreg:DF (match_dup 0) 0) (match_dup 1))
(set (subreg:DF (match_dup 0) 8) (match_dup 1))]
"
***************
*** 3658,3666 ****
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
! if (TARGET_VIS
! && GET_CODE (operands[1]) == CONST_DOUBLE
! && fp_zero_operand (operands[1]))
goto movtf_is_ok;
/* emit_group_store will send such bogosity to us when it is
--- 3643,3649 ----
if (GET_CODE (operands[0]) == REG
&& CONSTANT_P (operands[1]))
{
! if (TARGET_VIS && fp_zero_operand (operands[1], TFmode))
goto movtf_is_ok;
/* emit_group_store will send such bogosity to us when it is