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Re: MIPS patch submittion


Dmitri Makarov <dim@windriver.com> writes:

> The reason is that a MIPS special register, namely HI, is being allocated
> by reloader to mtime variable. Reloader generates an insn that doesn't 
> satisfy its constraines:
> 
> cc1: test.c: In function `ExecuteJava':
> test.c:2109: internal error--insn does not satisfy its constraints:
> 
> (insn 28897 28895 8899 (set (reg:SI 64 hi)
>         (reg:SI 2 v0)) 243 {movsi_internal2+1} (nil)
>     (nil))
> 
> This situation is caused by erroneous macro REGISTER_MOVE_COST, which
> includes code to prevent allocation of HI/LO/HILO to pseudos, but does 
> not.  The fix is the rewritten macro which does what it's intented to
> do.

I submitted a patch for this last month.  However, I just tried to find
the message in the archives and can't, so it seems it never made it; I
was having mail server difficulties at that time.  This was my patch,
for reference.  (I didn't change the macro to a function, although I
consider that a worthwile change.)

				-Clint

        * config/mips/mips.h (REGISTER_MOVE_COST): Remove redundant
        case for moving from HI/LO/HI_LO_REG.  This makes the behavior
        match the comment for MIPS16.

Index: mips.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.h,v
retrieving revision 1.82
diff -c -2 -p -r1.82 mips.h
*** mips.h	2000/01/11 17:42:30	1.82
--- mips.h	2000/01/13 21:58:20
*************** while (0)
*** 3706,3712 ****
     : (((FROM) == HI_REG || (FROM) == LO_REG				\
         || (FROM) == MD_REGS || (FROM) == HILO_REG)			\
-       && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6			\
-    : (((FROM) == HI_REG || (FROM) == LO_REG				\
-        || (FROM) == MD_REGS || (FROM) == HILO_REG)			\
        && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6)		\
     : (((TO) == HI_REG || (TO) == LO_REG					\
--- 3706,3709 ----

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