Re: patch to fix SH4 mode-switching problems

[Toshiyasu Morita <tm at netcom dot com>]

>   > All right, here is a draft list of macros / attributes:
>   > 
>   > FPSCR_USE_IN_EXIT_BLOCK
>   >  If this macro is defined, it is called for each exit block.  Its return
>   >  value should be the pattern of an insn.  It is emitted before the
>   >  return insn / use insns at the end of the exit block.
> You're missing the entire point.  FPSCR should not be appearing at
> all in the generic source.
> 
> Think at a higher level, please.
> 
> Conceptually you want the generic code to query the backend about whether or
> not an insn has a particular property.  The optimizer doesn't know or care
> about the property itself.
> 
> The property in your case is the state of fpscr, for another chip it
> might be the rounding mode of the FPU, or something completely unrelated.

I can think of at least one other processor which could use this type of
facility: the Western Design Center 65816. 

It's not currently supported by GCC, but it has two modal bits which 
determine the size of its accumulator and its two index registers.
(bits 5 and 6 in the P register) There's also two immediate-mode
instructions to set and reset bits in the P register as well.

These particular features made code generation extremely difficult for 
compilers, so there aren't many compilers which support it.

Toshi