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Re: Fixing the arm/thumb backends
- To: Bernd Schmidt <bernds at cygnus dot co dot uk>
- Subject: Re: Fixing the arm/thumb backends
- From: Richard Henderson <rth at cygnus dot com>
- Date: Thu, 7 Oct 1999 11:57:16 -0700
- Cc: gcc-patches at gcc dot gnu dot org, rearnsha at arm dot com
- References: <Pine.LNX.4.10.9910071827470.4509-100000@biriani.cygnus.co.uk>
On Thu, Oct 07, 1999 at 06:37:51PM +0100, Bernd Schmidt wrote:
> My question is, is this a change that is expected to be necessary
> due to the new genrecog?
It's quite possible. I'm really surprised at the number of
problems the new code is turning up that were supposed to
have been detected before.
> @@ -2086,8 +2086,11 @@ arm_rhs_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> - return (s_register_operand (op, mode)
> - || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
> + if (GET_CODE (op) == CONST_INT)
> + return const_ok_for_arm (INTVAL (op));
> + if (GET_MODE (op) != mode)
> + return FALSE;
> + return s_register_operand (op, mode);
You shouldn't need to make this change, as s_register_operand
should be checking the mode. Further, all mode checks should
allow mode==VOIDmode to match, as that is a signal that we don't
care about the mode of the operand.
> @@ -2098,9 +2101,11 @@ arm_rhsm_operand (op, mode)
> @@ -2111,10 +2116,12 @@ arm_add_operand (op, mode)
> @@ -2122,10 +2129,12 @@ arm_not_operand (op, mode)
> @@ -2302,9 +2321,11 @@ index_operand (op, mode)
> @@ -72,9 +72,11 @@ thumb_cmp_operand (op, mode)
Likewise.
> @@ -2199,10 +2208,12 @@ fpu_rhs_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> + if (GET_CODE (op) == CONST_DOUBLE)
> + return (const_double_rtx_ok_for_fpu (op));
> + if (GET_MODE (op) != mode)
> + return FALSE;
> if (s_register_operand (op, mode))
> return TRUE;
> - else if (GET_CODE (op) == CONST_DOUBLE)
> - return (const_double_rtx_ok_for_fpu (op));
You probably want to move the CONST_DOUBLE check after the
mode check. CONST_DOUBLE is VOIDmode for integers, but
uses the appropriate mode for FP constants.
> @@ -2212,12 +2223,14 @@ fpu_add_operand (op, mode)
Likewise.
> @@ -2246,6 +2259,9 @@ di_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> + if (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
> + return FALSE;
This is probably correct; it depends on the context.
> @@ -2316,9 +2337,11 @@ const_shift_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> - return (power_of_two_operand (op, mode)
> - || (immediate_operand (op, mode)
> - && (INTVAL (op) < 32 && INTVAL (op) > 0)));
> + if (GET_CODE (op) == CONST_INT)
> + return INTVAL (op) < 32 && INTVAL (op) > 0;
> + if (GET_MODE (op) != mode)
> + return FALSE;
> + return power_of_two_operand (op, mode);
This isn't right at all -- power_of_two_operand matches CONST_INT too.
> (define_insn "*call_insn"
> [(call (mem:SI (match_operand:SI 0 "" "X"))
> - (match_operand:SI 1 "" ""))]
> + (match_operand 1 "" ""))]
> "GET_CODE (operands[0]) == SYMBOL_REF"
> "bl\\t%a0"
> [(set_attr "length" "4")])
Oh dear -- you were trying to match a const_int here.
This is a bug in genrecog. I'll fix it.
r~