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rs6000 signed shifted immediates patch
- To: egcs-patches at egcs dot cygnus dot com
- Subject: rs6000 signed shifted immediates patch
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Wed, 12 May 1999 22:16:45 -0400
- Cc: Michael Meissner <meissner at cygnus dot com>
Richard Henderson noticed a nasty mistake I made in handling the
lis instruction in 64-bit mode. The following patch based on his patch
was applied. Because of compatibility and readability reasons, one needs
to allow either signed or unsigned representation of the sign-extended
quantity. This is going to conflict with some of the Cygnus PowerPC
changes which still are awaiting integration.
David
Sun May 9 14:57:47 1999 David Edelsohn <edelsohn@gnu.org>
Richard Henderson <rth@cygnus.com>
* rs6000.c (print_operand) [w]: Calculate signed constant more clearly.
(rs6000_allocate_stack_space): Print as hexadecimal value.
* rs6000.h (CONST_OK_FOR_LETTER_P): 'L' checks for a signed,
16-bit shifted constant. Fix typo for 'P'.
(EXTRA_CONSTARINT): 'T' checks for a 32-bit mask operand.
* rs6000.md (movsi, addsi3_internal1, movdi, adddi3_internal1):
Use 'L' for shifted constant.
(anddi3_internal3): Fix typo.
(32-bit mask patterns): Use 'T'.
Index: rs6000.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.68
diff -c -p -r1.68 rs6000.c
*** rs6000.c 1999/05/08 01:46:12 1.68
--- rs6000.c 1999/05/12 17:03:00
*************** print_operand (file, x, code)
*** 3063,3069 ****
{
int value = (INT_LOWPART (x) >> 16) & 0xffff;
! /* Solaris assembler doesn't like lis 0,0x80000 */
if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
fprintf (file, "%d", value | (~0 << 16));
else
--- 3063,3069 ----
{
int value = (INT_LOWPART (x) >> 16) & 0xffff;
! /* Solaris assembler doesn't like lis 0,0x8000 */
if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
fprintf (file, "%d", value | (~0 << 16));
else
*************** print_operand (file, x, code)
*** 3122,3129 ****
/* If constant, low-order 16 bits of constant, signed. Otherwise, write
normally. */
if (INT_P (x))
! fprintf (file, "%d",
! (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
else
print_operand (file, x, 0);
return;
--- 3122,3128 ----
/* If constant, low-order 16 bits of constant, signed. Otherwise, write
normally. */
if (INT_P (x))
! fprintf (file, "%d", ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
else
print_operand (file, x, 0);
return;
*************** rs6000_output_load_toc_table (file, reg)
*** 3915,3921 ****
reg_names[reg], reg_names[0], reg_names[reg]);
rs6000_pic_labelno++;
}
! else if (!TARGET_64BIT)
{
ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
asm_fprintf (file, "\t{liu|lis} %s,", reg_names[reg]);
--- 3914,3920 ----
reg_names[reg], reg_names[0], reg_names[reg]);
rs6000_pic_labelno++;
}
! else if (! TARGET_64BIT)
{
ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
asm_fprintf (file, "\t{liu|lis} %s,", reg_names[reg]);
*************** rs6000_allocate_stack_space (file, size,
*** 3959,3965 ****
if (copy_r12)
fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
! asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
asm_fprintf (file,
--- 3958,3964 ----
if (copy_r12)
fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
! asm_fprintf (file, "\t{liu|lis} %s,0x%x\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
asm_fprintf (file,
*************** rs6000_allocate_stack_space (file, size,
*** 3975,3981 ****
reg_names[1], neg_size, reg_names[1]);
else
{
! asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", reg_names[1],
--- 3974,3980 ----
reg_names[1], neg_size, reg_names[1]);
else
{
! asm_fprintf (file, "\t{liu|lis} %s,0x%x\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", reg_names[1],
*************** output_prolog (file, size)
*** 4211,4217 ****
{
int neg_size = info->main_save_offset - info->total_size;
loc = 0;
! asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
--- 4210,4216 ----
{
int neg_size = info->main_save_offset - info->total_size;
loc = 0;
! asm_fprintf (file, "\t{liu|lis} %s,0x%x\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
Index: rs6000.h
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.47
diff -c -p -r1.47 rs6000.h
*** rs6000.h 1999/05/08 01:46:13 1.47
--- rs6000.h 1999/05/12 17:03:00
*************** enum reg_class
*** 1087,1096 ****
C is the letter, and VALUE is a constant value.
Return 1 if VALUE is in the range specified by C.
! `I' is signed 16-bit constants
`J' is a constant with only the high-order 16 bits non-zero
`K' is a constant with only the low-order 16 bits non-zero
! `L' is a constant that can be placed into a mask operand
`M' is a constant that is greater than 31
`N' is a constant that is an exact power of two
`O' is the constant zero
--- 1087,1096 ----
C is the letter, and VALUE is a constant value.
Return 1 if VALUE is in the range specified by C.
! `I' is a signed 16-bit constant
`J' is a constant with only the high-order 16 bits non-zero
`K' is a constant with only the low-order 16 bits non-zero
! `L' is a signed 16-bit constant shifted left 16 bits
`M' is a constant that is greater than 31
`N' is a constant that is an exact power of two
`O' is the constant zero
*************** enum reg_class
*** 1100,1110 ****
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
: (C) == 'J' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
! : (C) == 'L' ? mask_constant (VALUE) \
: (C) == 'M' ? (VALUE) > 31 \
: (C) == 'N' ? exact_log2 (VALUE) >= 0 \
: (C) == 'O' ? (VALUE) == 0 \
! : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x1000 \
: 0)
/* Similar, but for floating constants, and defining letters G and H.
--- 1100,1111 ----
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
: (C) == 'J' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
! : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
! && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
: (C) == 'M' ? (VALUE) > 31 \
: (C) == 'N' ? exact_log2 (VALUE) >= 0 \
: (C) == 'O' ? (VALUE) == 0 \
! : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
: 0)
/* Similar, but for floating constants, and defining letters G and H.
*************** enum reg_class
*** 1126,1137 ****
--- 1127,1140 ----
'Q' means that is a memory operand that is just an offset from a reg.
'R' is for AIX TOC entries.
'S' is a constant that can be placed into a 64-bit mask operand
+ 'T' is a consatnt that can be placed into a 32-bit mask operand
'U' is for V.4 small data references. */
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
: (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
: (C) == 'S' ? mask64_operand (OP, VOIDmode) \
+ : (C) == 'T' ? mask_operand (OP, VOIDmode) \
: (C) == 'U' ? ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
&& small_data_operand (OP, GET_MODE (OP))) \
: 0)
Index: rs6000.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.53
diff -c -p -r1.53 rs6000.md
*** rs6000.md 1999/04/09 07:45:00 1.53
--- rs6000.md 1999/05/12 17:03:01
***************
*** 916,922 ****
(define_insn "*addsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
! (match_operand:SI 2 "add_operand" "r,I,I,J")))]
""
"@
{cax|add} %0,%1,%2
--- 916,922 ----
(define_insn "*addsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
! (match_operand:SI 2 "add_operand" "r,I,I,L")))]
""
"@
{cax|add} %0,%1,%2
***************
*** 1853,1859 ****
(define_insn "andsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
! (match_operand:SI 2 "and_operand" "?r,L,K,J")))
(clobber (match_scratch:CC 3 "=X,X,x,x"))]
""
"@
--- 1853,1859 ----
(define_insn "andsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
! (match_operand:SI 2 "and_operand" "?r,T,K,J")))
(clobber (match_scratch:CC 3 "=X,X,x,x"))]
""
"@
***************
*** 1870,1876 ****
(define_insn "*andsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
! (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
--- 1870,1876 ----
(define_insn "*andsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
! (match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
***************
*** 1907,1913 ****
(define_insn "*andsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
! (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
(and:SI (match_dup 1)
--- 1907,1913 ----
(define_insn "*andsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
! (match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
(and:SI (match_dup 1)
***************
*** 2908,2914 ****
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
! (match_operand:SI 3 "mask_operand" "L")))]
""
"{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
--- 2908,2914 ----
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
! (match_operand:SI 3 "mask_operand" "T")))]
""
"{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
***************
*** 2917,2923 ****
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
! (match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
""
--- 2917,2923 ----
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
! (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
""
***************
*** 2929,2935 ****
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
! (match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
--- 2929,2935 ----
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
! (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
***************
*** 3093,3099 ****
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "L")))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
--- 3093,3099 ----
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "T")))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
***************
*** 3102,3108 ****
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_lshift_p (operands[2], operands[3])"
--- 3102,3108 ----
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_lshift_p (operands[2], operands[3])"
***************
*** 3114,3120 ****
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
--- 3114,3120 ----
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
***************
*** 3216,3222 ****
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "L")))]
"includes_rshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
--- 3216,3222 ----
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "T")))]
"includes_rshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
***************
*** 3225,3231 ****
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_rshift_p (operands[2], operands[3])"
--- 3225,3231 ----
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_rshift_p (operands[2], operands[3])"
***************
*** 3237,3243 ****
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
--- 3237,3243 ----
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
! (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
***************
*** 4819,4825 ****
(define_insn "*adddi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
! (match_operand:DI 2 "add_operand" "r,I,I,J")))]
"TARGET_POWERPC64"
"@
add %0,%1,%2
--- 4819,4825 ----
(define_insn "*adddi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
! (match_operand:DI 2 "add_operand" "r,I,I,L")))]
"TARGET_POWERPC64"
"@
add %0,%1,%2
***************
*** 5475,5481 ****
and. %0,%1,%2
andi. %0,%1,%b2
andis. %0,%1,%u2
! rldic%B2. %3,%1,0,%S2"
[(set_attr "type" "compare,compare,compare,delayed_compare")])
(define_expand "iordi3"
--- 5475,5481 ----
and. %0,%1,%2
andi. %0,%1,%b2
andis. %0,%1,%u2
! rldic%B2. %0,%1,0,%S2"
[(set_attr "type" "compare,compare,compare,delayed_compare")])
(define_expand "iordi3"
***************
*** 5975,5981 ****
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
! (match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
"@
--- 5975,5981 ----
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
! (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
"@
***************
*** 6214,6220 ****
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
! (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
"@
--- 6214,6220 ----
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
! (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
"@
***************
*** 6601,6607 ****
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
! (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
--- 6601,6607 ----
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
! (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"