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More PA asm cleanups
- To: egcs-patches at egcs dot cygnus dot com
- Subject: More PA asm cleanups
- From: Jeffrey A Law <law at upchuck dot cygnus dot com>
- Date: Tue, 13 Apr 1999 13:04:27 -0600
- Reply-To: law at cygnus dot com
Amazing what you find when you use a stricter assembler :-) More cases
where we used a raw immediate instead of a register.
* pa.c: Use a register name, not a raw immediate in branch,
compare/clear, sub, subb, uaddcm and vshd instructions.
Index: pa.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/pa/pa.c,v
retrieving revision 1.33
diff -c -3 -p -r1.33 pa.c
*** pa.c 1999/04/13 11:31:31 1.33
--- pa.c 1999/04/13 19:05:58
*************** output_cbranch (operands, nullify, lengt
*** 4472,4478 ****
else
strcat (buf, "%S3");
if (useskip)
! strcat (buf, " %2,%r1,0");
else if (nullify)
strcat (buf, ",n %2,%r1,%0");
else
--- 4472,4478 ----
else
strcat (buf, "%S3");
if (useskip)
! strcat (buf, " %2,%r1,%%r0");
else if (nullify)
strcat (buf, ",n %2,%r1,%0");
else
*************** output_cbranch (operands, nullify, lengt
*** 4494,4500 ****
strcat (buf, "%S3");
else
strcat (buf, "%B3");
! strcat (buf, ",n %2,%r1,.+12\n\tbl %0,0");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a comb;nop rather than comiclr;bl saves 1 cycle for both
--- 4494,4500 ----
strcat (buf, "%S3");
else
strcat (buf, "%B3");
! strcat (buf, ",n %2,%r1,.+12\n\tb %0");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a comb;nop rather than comiclr;bl saves 1 cycle for both
*************** output_cbranch (operands, nullify, lengt
*** 4519,4527 ****
else
strcat (buf, "%B3");
if (nullify)
! strcat (buf, " %2,%r1,0\n\tbl,n %0,0");
else
! strcat (buf, " %2,%r1,0\n\tbl %0,0");
}
break;
--- 4519,4527 ----
else
strcat (buf, "%B3");
if (nullify)
! strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
else
! strcat (buf, " %2,%r1,%%r0\n\tb %0");
}
break;
*************** output_bb (operands, nullify, length, ne
*** 4654,4660 ****
else
strcat (buf, "<");
if (useskip)
! strcat (buf, " %0,%1,1,0");
else if (nullify && negated)
strcat (buf, ",n %0,%1,%3");
else if (nullify && ! negated)
--- 4654,4660 ----
else
strcat (buf, "<");
if (useskip)
! strcat (buf, " %0,%1,1,%%r0");
else if (nullify && negated)
strcat (buf, ",n %0,%1,%3");
else if (nullify && ! negated)
*************** output_bb (operands, nullify, length, ne
*** 4682,4690 ****
else
strcat (buf, ">=");
if (negated)
! strcat (buf, ",n %0,%1,.+12\n\tbl %3,0");
else
! strcat (buf, ",n %0,%1,.+12\n\tbl %2,0");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a bb;nop rather than extrs;bl saves 1 cycle for both
--- 4682,4690 ----
else
strcat (buf, ">=");
if (negated)
! strcat (buf, ",n %0,%1,.+12\n\tb %3");
else
! strcat (buf, ",n %0,%1,.+12\n\tb %2");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a bb;nop rather than extrs;bl saves 1 cycle for both
*************** output_bb (operands, nullify, length, ne
*** 4715,4727 ****
else
strcat (buf, ">=");
if (nullify && negated)
! strcat (buf, " %0,%1,1,0\n\tbl,n %3,0");
else if (nullify && ! negated)
! strcat (buf, " %0,%1,1,0\n\tbl,n %2,0");
else if (negated)
! strcat (buf, " %0,%1,1,0\n\tbl %3,0");
else
! strcat (buf, " %0,%1,1,0\n\tbl %2,0");
}
break;
--- 4715,4727 ----
else
strcat (buf, ">=");
if (nullify && negated)
! strcat (buf, " %0,%1,1,%%r0\n\tbn %3");
else if (nullify && ! negated)
! strcat (buf, " %0,%1,1,%%r0\n\tbn %2");
else if (negated)
! strcat (buf, " %0,%1,1,%%r0\n\tb %3");
else
! strcat (buf, " %0,%1,1,%%r0\n\tb %2");
}
break;
*************** output_bvb (operands, nullify, length, n
*** 4792,4798 ****
else
strcat (buf, "<");
if (useskip)
! strcat (buf, " %0,1,0");
else if (nullify && negated)
strcat (buf, ",n %0,%3");
else if (nullify && ! negated)
--- 4792,4798 ----
else
strcat (buf, "<");
if (useskip)
! strcat (buf, " %0,1,%%r0");
else if (nullify && negated)
strcat (buf, ",n %0,%3");
else if (nullify && ! negated)
*************** output_bvb (operands, nullify, length, n
*** 4820,4828 ****
else
strcat (buf, ">=");
if (negated)
! strcat (buf, ",n %0,.+12\n\tbl %3,0");
else
! strcat (buf, ",n %0,.+12\n\tbl %2,0");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a bb;nop rather than extrs;bl saves 1 cycle for both
--- 4820,4828 ----
else
strcat (buf, ">=");
if (negated)
! strcat (buf, ",n %0,.+12\n\tb %3");
else
! strcat (buf, ",n %0,.+12\n\tb %2");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a bb;nop rather than extrs;bl saves 1 cycle for both
*************** output_bvb (operands, nullify, length, n
*** 4853,4865 ****
else
strcat (buf, ">=");
if (nullify && negated)
! strcat (buf, " %0,1,0\n\tbl,n %3,0");
else if (nullify && ! negated)
! strcat (buf, " %0,1,0\n\tbl,n %2,0");
else if (negated)
! strcat (buf, " %0,1,0\n\tbl %3,0");
else
! strcat (buf, " %0,1,0\n\tbl %2,0");
}
break;
--- 4853,4865 ----
else
strcat (buf, ">=");
if (nullify && negated)
! strcat (buf, " %0,1,%%r0\n\tbn %3");
else if (nullify && ! negated)
! strcat (buf, " %0,1,%%r0\n\tbn %2");
else if (negated)
! strcat (buf, " %0,1,%%r0\n\tb %3");
else
! strcat (buf, " %0,1,%%r0\n\tb %2");
}
break;
*************** output_dbra (operands, insn, which_alter
*** 4928,4934 ****
if (dbr_sequence_length () != 0
&& ! forward_branch_p (insn)
&& nullify)
! return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
/* Handle short backwards branch with an unfilled delay slot.
Using a addb;nop rather than addi;bl saves 1 cycle for both
taken and untaken branches. */
--- 4928,4934 ----
if (dbr_sequence_length () != 0
&& ! forward_branch_p (insn)
&& nullify)
! return "addib,%N2,n %1,%0,.+12\n\tb %3";
/* Handle short backwards branch with an unfilled delay slot.
Using a addb;nop rather than addi;bl saves 1 cycle for both
taken and untaken branches. */
*************** output_dbra (operands, insn, which_alter
*** 4941,4949 ****
/* Handle normal cases. */
if (nullify)
! return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
else
! return "addi,%N2 %1,%0,%0\n\tbl %3,0";
}
else
abort();
--- 4941,4949 ----
/* Handle normal cases. */
if (nullify)
! return "addi,%N2 %1,%0,%0\n\tb,n %3";
else
! return "addi,%N2 %1,%0,%0\n\tb %3";
}
else
abort();
*************** output_dbra (operands, insn, which_alter
*** 4957,4965 ****
output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
if (get_attr_length (insn) == 24)
! return "comb,%S2 0,%4,%3\n\tfldws -16(%%r30),%0";
else
! return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(%%r30),%0";
}
/* Deal with gross reload from memory case. */
else
--- 4957,4965 ----
output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
if (get_attr_length (insn) == 24)
! return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
else
! return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
}
/* Deal with gross reload from memory case. */
else
*************** output_dbra (operands, insn, which_alter
*** 4970,4976 ****
if (get_attr_length (insn) == 12)
return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
else
! return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
}
}
--- 4970,4976 ----
if (get_attr_length (insn) == 12)
return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
else
! return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
}
}
*************** output_movb (operands, insn, which_alter
*** 5035,5041 ****
if (dbr_sequence_length () != 0
&& ! forward_branch_p (insn)
&& nullify)
! return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
/* Handle short backwards branch with an unfilled delay slot.
Using a movb;nop rather than or;bl saves 1 cycle for both
--- 5035,5041 ----
if (dbr_sequence_length () != 0
&& ! forward_branch_p (insn)
&& nullify)
! return "movb,%N2,n %1,%0,.+12\n\tb %3";
/* Handle short backwards branch with an unfilled delay slot.
Using a movb;nop rather than or;bl saves 1 cycle for both
*************** output_movb (operands, insn, which_alter
*** 5048,5056 ****
return "movb,%C2 %1,%0,%3%#";
/* Handle normal cases. */
if (nullify)
! return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
else
! return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
}
else
abort();
--- 5048,5056 ----
return "movb,%C2 %1,%0,%3%#";
/* Handle normal cases. */
if (nullify)
! return "or,%N2 %1,%%r0,%0\n\tb,n %3";
else
! return "or,%N2 %1,%%r0,%0\n\tb %3";
}
else
abort();
*************** output_movb (operands, insn, which_alter
*** 5063,5071 ****
the FP register from MEM from within the branch's delay slot. */
output_asm_insn ("stw %1,-16(%%r30)",operands);
if (get_attr_length (insn) == 12)
! return "comb,%S2 0,%1,%3\n\tfldws -16(%%r30),%0";
else
! return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(%%r30),%0";
}
/* Deal with gross reload from memory case. */
else if (which_alternative == 2)
--- 5063,5071 ----
the FP register from MEM from within the branch's delay slot. */
output_asm_insn ("stw %1,-16(%%r30)",operands);
if (get_attr_length (insn) == 12)
! return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
else
! return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
}
/* Deal with gross reload from memory case. */
else if (which_alternative == 2)
*************** output_movb (operands, insn, which_alter
*** 5073,5089 ****
/* Reload loop counter from memory, the store back to memory
happens in the branch's delay slot. */
if (get_attr_length (insn) == 8)
! return "comb,%S2 0,%1,%3\n\tstw %1,%0";
else
! return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
}
/* Handle SAR as a destination. */
else
{
if (get_attr_length (insn) == 8)
! return "comb,%S2 0,%1,%3\n\tmtsar %r1";
else
! return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tmtsar %r1";
}
}
--- 5073,5089 ----
/* Reload loop counter from memory, the store back to memory
happens in the branch's delay slot. */
if (get_attr_length (insn) == 8)
! return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
else
! return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
}
/* Handle SAR as a destination. */
else
{
if (get_attr_length (insn) == 8)
! return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
else
! return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
}
}
*************** output_millicode_call (insn, call_dest)
*** 5157,5163 ****
output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
/* Get our return address into %r31. */
! output_asm_insn ("blr 0,%%r31", xoperands);
/* Jump to our target address in %r29. */
output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
--- 5157,5163 ----
output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
/* Get our return address into %r31. */
! output_asm_insn ("blr %%r0,%%r31", xoperands);
/* Jump to our target address in %r29. */
output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
*************** output_call (insn, call_dest)
*** 5415,5421 ****
output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
/* Get the return address into %r31. */
! output_asm_insn ("blr 0,%%r31", xoperands);
/* Branch to our target which is in %r1. */
output_asm_insn ("bv %%r0(%%r1)", xoperands);
--- 5415,5421 ----
output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
/* Get the return address into %r31. */
! output_asm_insn ("blr %%r0,%%r31", xoperands);
/* Branch to our target which is in %r1. */
output_asm_insn ("bv %%r0(%%r1)", xoperands);
*************** output_parallel_movb (operands, length)
*** 5823,5839 ****
/* Nothing in the delay slot, fake it by putting the combined
insn (the copy or add) in the delay slot of a bl. */
if (GET_CODE (operands[1]) == CONST_INT)
! return "bl %2,0\n\tldi %1,%0";
else
! return "bl %2,0\n\tcopy %1,%0";
}
else
{
/* Something in the delay slot, but we've got a long branch. */
if (GET_CODE (operands[1]) == CONST_INT)
! return "ldi %1,%0\n\tbl %2,0";
else
! return "copy %1,%0\n\tbl %2,0";
}
}
--- 5823,5839 ----
/* Nothing in the delay slot, fake it by putting the combined
insn (the copy or add) in the delay slot of a bl. */
if (GET_CODE (operands[1]) == CONST_INT)
! return "b %2\n\tldi %1,%0";
else
! return "b %2\n\tcopy %1,%0";
}
else
{
/* Something in the delay slot, but we've got a long branch. */
if (GET_CODE (operands[1]) == CONST_INT)
! return "ldi %1,%0\n\tb %2";
else
! return "copy %1,%0\n\tb %2";
}
}
*************** output_parallel_addb (operands, length)
*** 5858,5869 ****
{
/* Nothing in the delay slot, fake it by putting the combined
insn (the copy or add) in the delay slot of a bl. */
! return "bl %3,0\n\tadd%I1 %1,%0,%0";
}
else
{
/* Something in the delay slot, but we've got a long branch. */
! return "add%I1 %1,%0,%0\n\tbl %3,0";
}
}
--- 5858,5869 ----
{
/* Nothing in the delay slot, fake it by putting the combined
insn (the copy or add) in the delay slot of a bl. */
! return "b %3\n\tadd%I1 %1,%0,%0";
}
else
{
/* Something in the delay slot, but we've got a long branch. */
! return "add%I1 %1,%0,%0\n\tb %3";
}
}
Index: pa.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/pa/pa.md,v
retrieving revision 1.26
diff -c -3 -p -r1.26 pa.md
*** pa.md 1999/04/13 11:31:35 1.26
--- pa.md 1999/04/13 19:06:06
***************
*** 3478,3484 ****
[(set (match_operand:DI 0 "register_operand" "=r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
""
! "sub 0,%R1,%R0\;subb 0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "8")])
--- 3478,3484 ----
[(set (match_operand:DI 0 "register_operand" "=r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
""
! "sub %%r0,%R1,%R0\;subb %%r0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "8")])
***************
*** 3486,3492 ****
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
! "sub 0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "4")])
--- 3486,3492 ----
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
! "sub %%r0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "4")])
***************
*** 3504,3510 ****
[(set (match_operand:DI 0 "register_operand" "=r")
(not:DI (match_operand:DI 1 "register_operand" "r")))]
""
! "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
[(set_attr "type" "unary")
(set_attr "length" "8")])
--- 3504,3510 ----
[(set (match_operand:DI 0 "register_operand" "=r")
(not:DI (match_operand:DI 1 "register_operand" "r")))]
""
! "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
[(set_attr "type" "unary")
(set_attr "length" "8")])
***************
*** 3512,3518 ****
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
! "uaddcm 0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "4")])
--- 3512,3518 ----
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
! "uaddcm %%r0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "4")])
***************
*** 3877,3883 ****
(match_operand:SI 2 "arith32_operand" "q,n")))]
""
"@
! vshd 0,%1,%0
extru %1,%P2,%L2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
--- 3877,3883 ----
(match_operand:SI 2 "arith32_operand" "q,n")))]
""
"@
! vshd %%r0,%1,%0
extru %1,%P2,%L2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])