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Re: x86 ashlsi3 improvements
- To: Jan Hubicka <hubicka at horac dot ta dot jcu dot cz>
- Subject: Re: x86 ashlsi3 improvements
- From: Jeffrey A Law <law at hurl dot cygnus dot com>
- Date: Tue, 09 Mar 1999 01:18:35 -0700
- cc: egcs-patches at egcs dot cygnus dot com
- Reply-To: law at cygnus dot com
In message <19990218101301.A16285@horac.ta.jcu.cz>you write:
> I've done some benchmarking here and win of lea over sal is not clear.
Neither is going to be perfect. I'm sure we can both point point to codes
which perform better with one code generation strategy or another if given a
little time. The goal is to have something that is generally better, and
which will continue to improve over time as we improve scheduling for the
Pentium and PPro/PII processors.
> You need to take into account important property of lea - it is executed
> in operand fetch pass, so its operands have memory adress behaviour - they
> need to be ready one cycle before lea is executed otherwise AGI stall
Yes. I'm aware of AGI stalls.
One thing we can do to mitigate this would be to use a shift instruction if the
instruction is believed to be the first in an issue bundle. This can be
determined by looking at the mode of the insn. If it is not TImode, then the
insn is expected to be the 1st insn in an issue bundle, meaning it is expected
to issue into the U pipe and we should use sal over lea.
This will avoid many of the AGI stalls, and over time as the x86 port improves
in terms of Pentium scheduling this scheme will improve along the way too.