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Re: ppc patch



  In message <9808230305.AA24082@marc.watson.ibm.com>you write:
  > 	The movdf patterns use %L print_operand case for the
  > register/memory pair.  This case *cannot* handle indexed addressing.  I
  > think the 'o' was trying to prevent indexed addressing when a memory pair
  > is necessary.
  > 
  > 	The problem is that by the time the compiler gets to the output
  > template, adding a constant increment to reference the neighboring memory
  > location is easy as long as the original reference included an offset that
  > was zero or constant.  If the offset was a register, i.e. an indexed
  > address, we cannot add another increment without inserting an additional
  > instruction.
Ah.  Yes, other ports deal with this by adding a couple instructions to
access the second word by adjusting the base register before and after
the memory access.  Gross, but effective.

  > 	Is there any way to prevent indexed addressing when
  > HARD_REGNO_NREGS is greater than 1 for the hard registers allocated?
  > I.e., indexing is not okay when DFmode is assigned to two 32-bit GPRs, but
  > is fine with FPRs.  The PRE_INC / PRE_DEC is fine, but indexing is not.
  > We have to allow DFmode in GPRs, not just for soft-float.
Nope.  The validity of an addressing mode is based solely on the address
and the mode of the memory access.

Michael Hayes has done some work to improve this situation, but I 
haven't looked at his stuff in any detail yet.



jeff


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