Re: Memory model release/acquire mode interactions of relaxed atomic operations

[Andrew Haley <aph at redhat dot com>]

On 04/05/17 12:46, Toebs Douglass wrote:
> On 04/05/17 13:20, Jonathan Wakely wrote:
>> On 4 May 2017 at 10:24, Toebs Douglass wrote:
>>> Atomic in this context, I believe, actually only really means the
>>> absence of word-tearing; you won't write half your int and then get
>>> swapped out and then write the other half later.
>>
>> No, "atomic" in the C++ memory model has a specific meaning, more than
>> just guaranteeing no word-tearing. Even on a CPU architecture where
>> word-tearing is impossible, the use of atomic operations rather than
>> non-atomic ones gives information to the compiler that affects the
>> semantics.
> 
> Inherently volatile, kindafing?  lay off the optimisation and caching in
> registers, etc?

Much stronger than volatile.

C++ atomic types are sequentially consistent by default.  Every
processor sees memory as if the atomic loads and stores of all the
processors had been executed in some sequential order.  Every
processor sees that same total ordering.  GCC will throw in as many
barrier instructions as are necessary to make that work.

Andrew.