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Re: mlock in cache
- From: Oleg Endo <oleg dot endo at t-online dot de>
- To: Christos <xristos dot tsop at gmail dot com>
- Cc: GCC-help <gcc-help at gcc dot gnu dot org>
- Date: Fri, 02 Aug 2013 20:14:24 +0200
- Subject: Re: mlock in cache
- References: <51FBBE65 dot 2000406 at gmail dot com> <51FBC1DE dot 3000501 at redhat dot com> <51FBCA48 dot 20106 at gmail dot com> <51FBCE48 dot 6080402 at redhat dot com> <51FBD281 dot 2040803 at gmail dot com> <51FBD309 dot 7000204 at redhat dot com> <51FBD595 dot 4020703 at gmail dot com> <CANjXV6-jOeCusNT3iZjNbGKdy0+B=TUwjmgJuBoUfpaUZRMCXQ at mail dot gmail dot com> <51FBE511 dot 7030505 at gmail dot com>
On Fri, 2013-08-02 at 17:57 +0100, Christos wrote:
> On 08/02/2013 05:38 PM, Brian Budge wrote:
> >
> > Can I naively ask what the purpose is of forcing this data to be in
> > cache all the time? If you use the data often enough for this to be
> > useful, it will already be in cache. If you don't, you benefit by
> > having it not be in cache.
> Many specific reasons. For example, if you want to tackle cold boot
> attacks on cryptographic keys
> you can either put you keys on some registers (there is a related
> implementation named tresor) or
> you can hide it the cache for example and force the opponent to dump the
> whole memory and synchronize
> the cache with the memory (which some times might not be possible).
>
> However, I generally consider the question of high academic interest.
I'd say the available options depend on the processor architecture.
Maybe it's better in your case to look at different architectures and
not at the types of built-ins GCC has or doesn't have. For example, the
SH4 CPU has some cache control instructions (not all of them are
available through GCC built-in functions):
movca.l - Reserves a cache line by marking it as valid for the specified
address. Does not synchronize it with memory if it is dirty.
ocbp - Write back and invalidate operand cache line
ocbwb - Write back cache line but do not invalidate it
pref - Prefetch cache line (no operation if it is already in the cache)
In addition to that, memory accesses can either go through the cache or
bypass the cache (there are special bits in the address for that when
accessing memory without MMU, or settings in MMU pages).
With these low level things something like what you described above
could be constructed, but probably it will be difficult to do so in a
multi tasking environment. If GCC doesn't have a built-in function
ready for the particular special instruction it can be issued rather
easily with inline asm. Also, there's no guarantee that e.g.
__builtin_prefetch will actually emit a prefetch instruction.
Cheers,
Oleg