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Re: floats / Porting GCC on a new arch
- From: Kai Ruottu <kai dot ruottu at wippies dot com>
- To: Florent DEFAY <spira dot inhabitant at gmail dot com>
- Cc: gcc-help at gcc dot gnu dot org
- Date: Wed, 25 Feb 2009 13:29:59 +0200
- Subject: Re: floats / Porting GCC on a new arch
- References: <8502af3c0902250258s1eaa66d7m6d8398456bd6075d@mail.gmail.com>
Florent DEFAY wrote:
My target machine doesn't support floats operations
> so I defined these macros :
#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
#undef TARGET_DECIMAL_FLOAT_SUPPORTED_P
#define TARGET_DECIMAL_FLOAT_SUPPORTED_P target_decimal_float_supported_p
// returns always false
#undef TARGET_FIXED_POINT_SUPPORTED_P
#define TARGET_FIXED_POINT_SUPPORTED_P target_fixed_point_supported_p
// returns always false
and that's all about floats.
What should I additionally implement ?
The normal way with no-FPU CPUs seems to be to use the
'config/fp-bit.c' which implements the basic soft-float
routines in C. These routines then will be a part of the
'libgcc.a', the "GCC helper library". Another way is to
implement these in the opsys kernel like in x86 with the
old i386, i486SX, "embedded x86" etc. "no-*87 FPU inside"
CPUs in the Linux kernel. The idea being that there could
be that FPU in the system but when there isn't, every float
opcode causes a "trap" or "exception" which the opsys kernel
will handle... Third way is to implement the soft-float ops
in the C library, I remember in Linux/PPC this being the
case, the 'glibc' for it includes the soft-float operations.
But with embedded "no FPU anywhere" CPUs the 'libgcc.a'
normally has those basic soft-float routines for add/sub/mul/div
for floats and doubles... Just "spy" the already ported
CPUs, their "target Makefile-fragments", the 't-<cpu>' or
something files in 'gcc/config/<cpu>'...