This is the mail archive of the
gcc-help@gcc.gnu.org
mailing list for the GCC project.
Re: GCC asm block optimizations on x86_64
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: "Darryl L. Miles" <darryl-mailinglists at netbauds dot net>
- Cc: gcc-help at gcc dot gnu dot org
- Date: Mon, 27 Aug 2007 10:31:49 +0200
- Subject: Re: GCC asm block optimizations on x86_64
- References: <46D25CE8.1070206@netbauds.net>
On Mon, Aug 27, 2007 at 06:11:04AM +0100, Darryl L. Miles wrote:
>
> [1] This issue is in the way %edx is zero'ed, I would think zeroing out
> registers/memory/whatever would be a special optimization case in this
> code its clear that there is no useful value in the CPU condition flags,
> so "xorl %edx,%edx" would make most sense, instead of having to find
> another register to load with zero before then copying. Interestingly
> enough -O generates a "mov $0,%r8d", while -O2 generates a "xor %r8d,%r8d".
Peephole optimization isn't performed at -O.
It is usually better to post asm output from "gcc -S -dp" than "objdump
--disassemble" output because the former shows which instruction pattern GCC
is using.
--
Rask Ingemann Lambertsen