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Re: Porting gcc to new core
- From: llewelly at xmission dot com
- To: Balaji S <sivanbalaji at acmet dot com>
- Cc: gcc-help at gcc dot gnu dot org
- Date: 20 May 2004 23:35:44 -0600
- Subject: Re: Porting gcc to new core
- References: <40AC635B.1060103@acmet.com>
Balaji S <sivanbalaji@acmet.com> writes:
> I am working on porting gcc to a core with the following characteristics:
> 1. Orthogonal and irregular (as ix86) byte register set
> 2. Pipelined RISC with blocking loads and no delay slots
> 3. Can load/store byte/half word/word/double word memory into register(s)
> 4. Segmented memory
>
> does anybody know/guide/point the reference architecture already ported with similar characteristics.
I think this question is more appropriate for gcc dot gnu dot org.