[gcc r10-6549] arm: correct constraints on movsi_compare0 [PR91913]

[Richard Earnshaw <rearnsha at gcc dot gnu dot org>]

https://gcc.gnu.org/g:1cad5e89a9e1b4ffa47bc6e3551643b342f6cfe8

commit r10-6549-g1cad5e89a9e1b4ffa47bc6e3551643b342f6cfe8
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Mon Feb 10 15:37:23 2020 +0000

    arm: correct constraints on movsi_compare0 [PR91913]
    
    The peephole that detects a mov of one register to another followed by
    a comparison of the original register against zero is only used in Arm
    state; but the instruction that matches this is generic to all 32-bit
    compilation states.  That instruction lacks support for SP which is
    permitted in Arm state, but has restrictions in Thumb2 code.
    
    This patch fixes the problem by allowing SP when in ARM state for all
    registers; in Thumb state it allows SP only as a source when the
    register really is copied to another target.
    
    	* config/arm/arm.md (movsi_compare0): Allow SP as a source register
    	in Thumb state and also as a destination in Arm state.  Add T16
    	variants.

Diff:
---
 gcc/ChangeLog         |  7 +++++++
 gcc/config/arm/arm.md | 11 ++++++++---
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a5c24db..60bd347 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2020-02-10  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/91913
+	* config/arm/arm.md (movsi_compare0): Allow SP as a source register
+	in Thumb state and also as a destination in Arm state.  Add T16
+	variants.
+
 2020-02-10  Hans-Peter Nilsson  <hp@axis.com>
 
 	* md.texi (Define Subst): Match closing paren in example.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5baf82d..ab27799 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6627,16 +6627,21 @@
 
 (define_insn "*movsi_compare0"
   [(set (reg:CC CC_REGNUM)
-	(compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
+	(compare:CC (match_operand:SI 1 "s_register_operand" "0,0,l,rk,rk")
 		    (const_int 0)))
-   (set (match_operand:SI 0 "s_register_operand" "=r,r")
+   (set (match_operand:SI 0 "s_register_operand" "=l,rk,l,r,rk")
 	(match_dup 1))]
   "TARGET_32BIT"
   "@
    cmp%?\\t%0, #0
+   cmp%?\\t%0, #0
+   subs%?\\t%0, %1, #0
+   subs%?\\t%0, %1, #0
    subs%?\\t%0, %1, #0"
   [(set_attr "conds" "set")
-   (set_attr "type" "alus_imm,alus_imm")]
+   (set_attr "arch" "t2,*,t2,t2,a")
+   (set_attr "type" "alus_imm")
+   (set_attr "length" "2,4,2,4,4")]
 )
 
 ;; Subroutine to store a half word from a register into memory.