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r242294 - in /branches/ARM/sve-branch/gcc/confi...


Author: rsandifo
Date: Fri Nov 11 17:35:18 2016
New Revision: 242294

URL: https://gcc.gnu.org/viewcvs?rev=242294&root=gcc&view=rev
Log:
[AArch64] Remove use of wider vector modes

The AArch64 port defined x2, x3 and x4 vector modes that were only used
in the rtl for the AdvSIMD LD{2,3,4} patterns.  It seems unlikely that
this rtl would have led to any valid simplifications, since the values
involved were unspecs that had a different number of operands from the
non-dreg versions.  (The dreg UNSPEC_LD2 had a single operand, while
the qreg one had two operands.)

As it happened, the patterns led to invalid simplifications on big-
endian targets due to a mix-up in the operand order, see Tamar's fix
in r240271.

This patch therefore replaces the rtl patterns with dedicated unspecs.
This allows the x2, x3 and x4 modes to be removed, avoiding a clash
with 256-bit and 512-bit SVE.

Modified:
    branches/ARM/sve-branch/gcc/config/aarch64/aarch64-modes.def
    branches/ARM/sve-branch/gcc/config/aarch64/aarch64-simd.md
    branches/ARM/sve-branch/gcc/config/aarch64/aarch64.md
    branches/ARM/sve-branch/gcc/config/aarch64/iterators.md


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