[Bug rtl-optimization/83530] [7/8 Regression] ICE in reset_sched_cycles_in_current_ebb, at sel-sched.c:7150

["abel at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83530

--- Comment #11 from Andrey Belevantsev <abel at gcc dot gnu.org> ---
I've made a deeper comparison with what the Haifa does.  We diverge because the
loop in reset_sched_cycles only models resource stalls and relies on the
information from the earlier scheduling pass for data stalls.  However, there
is no such information in this case as the loop was scheduled with the modulo
scheduler.

I need to think more on how this was supposed to work.  (Maybe the issue just
wasn't caught before just because we almost have no testing of modulo sched +
selective scheduler combination.  There is a single test of pr42388.)  If we
indeed do also need to model data stalls, it is easy to piggyback on the
sel-sched infrastructure in this case to make the scheduling but just to select
the next insn always for the BB_DISABLE_SCHEDULE blocks.  I've verified that
such a patch works.  Similarly, adding -freschedule-modulo-scheduled-blocks
makes the ICE disappear.

The initial patch that needs to be cleaned up (if the above is correct) is
like:

diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index 76092f9587a..fcdc2e7102e 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -5004,12 +5013,14 @@ remove_temp_moveop_nops (bool full_tidying)
    distinguishing between bookkeeping copies and original insns.  */
 static int max_uid_before_move_op = 0;

+static int force_next_insn = 0;
+
 /* Remove from AV_VLIW_P all instructions but next when debug counter
    tells us so.  Next instruction is fetched from BNDS.  */
 static void
 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
 {
-  if (! dbg_cnt (sel_sched_insn_cnt))
+  if (! dbg_cnt (sel_sched_insn_cnt) || force_next_insn)
     /* Leave only the next insn in av_vliw.  */
     {
       av_set_iterator av_it;
@@ -7642,7 +7653,13 @@ sel_sched_region (int rgn)
     sel_sched_region_1 ();
   else
     /* Force initialization of INSN_SCHED_CYCLEs for correct bundling.  */
-    reset_sched_cycles_p = true;
+    {
+      reset_sched_cycles_p = false;
+      pipelining_p = false;
+      force_next_insn = 1;
+      sel_sched_region_1 ();
+      force_next_insn = 0;
+    }

   sel_region_finish (reset_sched_cycles_p);
 }