[Bug rtl-optimization/84071] [7/8 regression] wrong elimination of zero-extension after sign-extended load

["mpf at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84071

mpf at gcc dot gnu.org changed:

           What    |Removed                     |Added
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                 CC|                            |mpf at gcc dot gnu.org

--- Comment #21 from mpf at gcc dot gnu.org ---
(In reply to Eric Botcazou from comment #20)
> > How is this any different from 32-bit operations in say MIPS? The only
> > difference seems to be that MIPS sign-extends 32-bit operations to 64 bit
> > while AArch64 zero-extends. If that's correct for MIPS it seems that
> > WORD_REGISTER_OPERATIONS only applies to types smaller than SImode.
> 
> Interesting question.  One indeed could argue that, if 64-bit MIPS defines
> it, then Aarch64 could do it too since they are symmetric wrt
> sign/zero-extension
> but I don't have a definitive answer as I don't really know the history of
> WORD_REGISTER_OPERATIONS on MIPS.

I believe the critical part for MIPS is that our 32-bit instructions do care
what the upper 32-bits of a 64-bit register contain. It is undefined if they
operate on a non-canonical 32-bit form and the instructions that are width
agnostic (conditional branch and logical ops) rely on canonical forms to work
correctly with 32-bit values.

So MIPS fundamentally needs this feature to work correctly; whether AArch64
needs it or may just benefit from it depends on a lot of detailed knowledge of
the ISA and architecture. Given Richard Sandiford is currently working on ARM
ports but also fully understands the MIPS arch then he may be a good person to
consult.