[Bug target/83850] [8 Regression] Spills on vector extract, gcc.target/i386/pr80846-1.c FAILs

["rguenth at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83850

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rsandifo at gcc dot gnu.org

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
(insn 16 15 18 4 (set (reg:V8SI 107)
        (plus:V8SI (subreg:V8SI (reg:V16SI 94 [ vect_sum_11.4 ]) 32)
            (subreg:V8SI (reg:V16SI 94 [ vect_sum_11.4 ]) 0))) 3004 {*addv8si3}
     (expr_list:REG_DEAD (reg:V16SI 94 [ vect_sum_11.4 ])
        (nil)))
...

         Choosing alt 1 in insn 16:  (0) v  (1) v  (2) vm {*addv8si3}
            alt=0: Bad operand -- refuse
            alt=1: Bad operand -- refuse

and then it somehow chooses to spill them rather than not spilling but
code-generating them into a reg?

The lowpart subreg is immediately available and the higpart subreg is
supported by the target as well.  The target originally was supposed to
generate code through

(define_expand "vec_extract<mode><ssehalfvecmodelower>"
  [(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
   (match_operand:V_512 1 "register_operand")
   (match_operand 2 "const_0_to_1_operand")]
  "TARGET_AVX512F"
{
  if (INTVAL (operands[2]))
    emit_insn (gen_vec_extract_hi_<mode> (operands[0], operands[1]));
  else
    emit_insn (gen_vec_extract_lo_<mode> (operands[0], operands[1]));
  DONE;
})

which ends up with a vec_select.  But somehow even .expand already shows

(insn 16 15 17 (set (reg:V8SI 107)
        (plus:V8SI (subreg:V8SI (reg:V16SI 94 [ vect_sum_11.4 ]) 32)
            (subreg:V8SI (reg:V16SI 94 [ vect_sum_11.4 ]) 0))) -1
     (nil))

For some reason we're not going into

  /* First try to check for vector from vector extractions.  */
  if (VECTOR_MODE_P (GET_MODE (op0))
      && !MEM_P (op0)
      && VECTOR_MODE_P (tmode)
      && known_eq (bitsize, GET_MODE_SIZE (tmode))
      && maybe_gt (GET_MODE_SIZE (GET_MODE (op0)), GET_MODE_SIZE (tmode)))
    {

anymore.

(gdb) p debug_rtx (op0)
(reg:V16SI 94 [ vect_sum_11.4 ])
(gdb) p bitsize
$11 = {<poly_int_pod<1u, unsigned long>> = {coeffs = {256}}, <No data fields>}
(gdb) p tmode
$12 = E_V8SImode

so GET_MODE_SIZE (tmode) returns 32 here.  That looks like a change in
behavior?  Richard?