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[Bug target/82445] ARM target generates unaligned STRD instruction
- From: "agraf at suse dot de" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 06 Oct 2017 10:02:24 +0000
- Subject: [Bug target/82445] ARM target generates unaligned STRD instruction
- Auto-submitted: auto-generated
- References: <bug-82445-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445
--- Comment #2 from Alexander Graf <agraf at suse dot de> ---
(In reply to Richard Biener from comment #1)
> Does -fno-store-merging fix it?
Yes, but it generates worse code than -march=armv5 (which does not support
STRD) does:
-march=armv6 -fno-store-merging:
> 00000000 <x>:
> 0: e59f3028 ldr r3, [pc, #40] ; 30 <x+0x30>
> 4: e3a02008 mov r2, #8
> 8: e3a0c010 mov ip, #16
> c: e3a00000 mov r0, #0
> 10: e3e01002 mvn r1, #2
> 14: e5933000 ldr r3, [r3]
> 18: e1c3c0b6 strh ip, [r3, #6]
> 1c: e1c300b8 strh r0, [r3, #8]
> 20: e1c310ba strh r1, [r3, #10]
> 24: e1c320b4 strh r2, [r3, #4]
> 28: e1c320bc strh r2, [r3, #12]
> 2c: e12fff1e bx lr
> 30: 00000000 .word 0x00000000
-march=armv5:
> 00000000 <x>:
> 0: e59f3018 ldr r3, [pc, #24] ; 20 <x+0x20>
> 4: e3a02008 mov r2, #8
> 8: e59f0014 ldr r0, [pc, #20] ; 24 <x+0x24>
> c: e59f1014 ldr r1, [pc, #20] ; 28 <x+0x28>
> 10: e5933000 ldr r3, [r3]
> 14: e9830003 stmib r3, {r0, r1}
> 18: e1c320bc strh r2, [r3, #12]
> 1c: e12fff1e bx lr
> 20: 00000000 .word 0x00000000
> 24: 00100008 .word 0x00100008
> 28: fffd0000 .word 0xfffd0000