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[Bug target/46091] missed optimization: x86 bt/btc/bts instructions
- From: "ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Mon, 14 Aug 2017 17:04:51 +0000
- Subject: [Bug target/46091] missed optimization: x86 bt/btc/bts instructions
- Auto-submitted: auto-generated
- References: <bug-46091-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46091
--- Comment #7 from Uroš Bizjak <ubizjak at gmail dot com> ---
From i386.md:
;; %%% bts, btr, btc, bt.
;; In general these instructions are *slow* when applied to memory,
;; since they enforce atomic operation. When applied to registers,
;; it depends on the cpu implementation. They're never faster than
;; the corresponding and/ior/xor operations, so with 32-bit there's
;; no point. But in 64-bit, we can't hold the relevant immediates
;; within the instruction itself, so operating on bits in the high
;; 32-bits of a register becomes easier.