[Bug rtl-optimization/81434] AArch64 instruction fusing and pipeline scheduling problem

["pinskia at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81434

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

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                 CC|                            |pinskia at gcc dot gnu.org

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to jim.wilson from comment #7) 
> If we represent a fused pair as a single instruction, then we are
> getting the issue count wrong, as they take two issue slots, but one
> function unit slot.

It depends on how the fusion works.  On the processor I am working on, the
fused instruction will take only one issue slot but two decode slots.

>  However, there is a way to deal with the issue
> count.  We could use TARGET_SCHED_VARIABLE_ISSUE to make the single
> fused insn take two issue slots.  I already wrote a patch like that
> for a different reason as an experiment so I know this can work.

If this is done, please make it dependent on the micro-arch.

I have another issue which I am trying to figure out how to handle.  In some
cases, the instructions don't take up an issue slots at all and their latency
are zero but only if one of those per dispatch group.