[Bug rtl-optimization/81434] AArch64 instruction fusing and pipeline scheduling problem

["jim.wilson at linaro dot org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81434

--- Comment #5 from jim.wilson at linaro dot org ---
On Wed, Jul 19, 2017 at 4:25 AM, wilco at gcc dot gnu.org
<gcc-bugzilla@gcc.gnu.org> wrote:
> To more accurately schedule fusion pairs wouldn't we need to specify the
> scheduling behaviour of the group as well? From the dumps below it schedules
> the adrp/add in the same cycle if we're lucky, but it is modelled as using 2
> ALUs rather than a new single fused instruction.

The fusion pair takes two issue slots and uses one alu, but is modeled
as taking two issues slots and using two alus.  I haven't tried to
address this problem.  I'm just trying to get the issue slot handling
correct for now, so that they can issue in the same cycle.

> Also is your change fixing the issue that the scheduler cannot schedule 2
> instructions with a zero latency dependency between them in the same cycle?
> That's a very similar bug.

The scheduler can schedule 2 insns w/ zero latency dependency in the
same cycle.  However, it does not do so when a SCHED_GROUP is
involved.  This is the bug that my patch fixes.

Jim