[Bug target/79799] Improve vec_insert of float on Power9

["meissner at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79799

--- Comment #3 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Thu Jun 29 22:19:29 2017
New Revision: 249819

URL: https://gcc.gnu.org/viewcvs?rev=249819&root=gcc&view=rev
Log:
[gcc]
2017-06-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

        Backport from mainline
        2017-06-23  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/80510
        * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in
        32-bit, since indexed is not valid for DImode.
        (mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA
        3.0 d-form load/stores to be the same as mov<mode>_hardfloat64.
        (define_peephole2 for Altivec d-form load): Add 32-bit support.
        (define_peephole2 for Altivec d-form store): Likewise.

        Backport from mainline
        2017-06-20  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/79799
        * config/rs6000/rs6000.c (rs6000_expand_vector_init): Add support
        for doing vector set of SFmode on ISA 3.0.
        * config/rs6000/vsx.md (vsx_set_v4sf_p9): Likewise.
        (vsx_set_v4sf_p9_zero): Special case setting 0.0f to a V4SF
        element.
        (vsx_insert_extract_v4sf_p9): Add an optimization for inserting a
        SFmode value into a V4SF variable that was extracted from another
        V4SF variable without converting the element to double precision
        and back to single precision vector format.
        (vsx_insert_extract_v4sf_p9_2): Likewise.

[gcc/testsuite]
2017-06-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

        Backport from mainline
        2017-06-23  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/80510
        * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit.
        * gcc.target/powerpc/pr80510-2.c: Likewise.

        Backport from mainline
        2017-06-20  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/79799
        * gcc.target/powerpc/pr79799-1.c: New test.
        * gcc.target/powerpc/pr79799-2.c: Likewise.
        * gcc.target/powerpc/pr79799-3.c: Likewise.
        * gcc.target/powerpc/pr79799-4.c: Likewise.
        * gcc.target/powerpc/pr79799-5.c: Likewise.


Added:
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr79799-1.c
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr79799-2.c
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr79799-3.c
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr79799-4.c
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr79799-5.c
Modified:
    branches/gcc-7-branch/gcc/ChangeLog
    branches/gcc-7-branch/gcc/config/rs6000/rs6000.c
    branches/gcc-7-branch/gcc/config/rs6000/rs6000.md
    branches/gcc-7-branch/gcc/config/rs6000/vsx.md
    branches/gcc-7-branch/gcc/testsuite/ChangeLog
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr80510-1.c
    branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr80510-2.c